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AM572x
Sitara™ Processors
Silicon Revision 2.0, 1.1
Texas Instruments Sitara™ Family of Products
Technical Reference Manual
Literature Number: SPRUHZ6G
October 2014–Revised June 2016
2
SPRUHZ6G–October 2014–Revised June 2016
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Copyright © 2014–2016, Texas Instruments Incorporated
Contents
Contents
Revision History ........................................................................................................................ 360
Preface..................................................................................................................................... 361
1 Introduction ..................................................................................................................... 369
1.1 AM572x Overview ........................................................................................................ 370
1.2 AM572x Environment .................................................................................................... 372
1.3 AM572x Description ...................................................................................................... 373
1.3.1 MPU Subsystem ................................................................................................. 374
1.3.2 DSP Subsystems ................................................................................................ 374
1.3.3 PRU-ICSS ........................................................................................................ 374
1.3.4 IPU Subsystems ................................................................................................. 374
1.3.5 IVA-HD Subsystem .............................................................................................. 375
1.3.6 Display Subsystem .............................................................................................. 375
1.3.7 Video Processing Subsystem .................................................................................. 376
1.3.8 Video Capture .................................................................................................... 376
1.3.9 3D GPU Subsystem ............................................................................................ 376
1.3.10 BB2D Subsystem ............................................................................................... 377
1.3.11 On-Chip Debug Support ....................................................................................... 377
1.3.12 Power, Reset, and Clock Management...................................................................... 378
1.3.13 On-Chip Memory................................................................................................ 378
1.3.14 Memory Management .......................................................................................... 378
1.3.15 External Memory Interfaces ................................................................................... 378
1.3.16 System and Connectivity Peripherals ........................................................................ 379
1.3.16.1 System Peripherals........................................................................................ 379
1.3.16.2 Media Connectivity Peripherals.......................................................................... 379
1.3.16.3 Connectivity Peripherals.................................................................................. 380
1.3.16.4 Audio Connectivity Peripherals .......................................................................... 380
1.3.16.5 Serial Control Peripherals ................................................................................ 380
1.4 AM572x Family............................................................................................................ 381
1.5 AM572x Device Identification ........................................................................................... 381
1.6 AM572x Package Characteristics Overview .......................................................................... 383
2 Memory Mapping .............................................................................................................. 384
2.1 Introduction ................................................................................................................ 385
2.2 L3_MAIN Memory Map .................................................................................................. 388
2.2.1 L3_INSTR Memory Map ........................................................................................ 391
2.3 L4 Memory Map........................................................................................................... 393
2.3.1 L4_CFG Memory Map .......................................................................................... 393
2.3.2 L4_WKUP Memory Map ........................................................................................ 396
2.3.3 L4_PER Memory Map........................................................................................... 398
2.3.3.1 L4_PER1 Memory Map................................................................................... 398
2.3.3.2 L4_PER2 Memory Map................................................................................... 400
2.3.3.3 L4_PER3 Memory Map................................................................................... 402
2.4 MPU Memory Map........................................................................................................ 405
2.5 IPU Memory Map ......................................................................................................... 407
2.6 DSP Memory Map ........................................................................................................ 408
2.7 EVE Memory Map ........................................................................................................ 408
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Contents
2.8 PRU-ICSS Memory Map................................................................................................. 409
2.9 TILER View Memory Map ............................................................................................... 410
3 Power, Reset, and Clock Management................................................................................. 411
3.1 Device Power Management Introduction .............................................................................. 412
3.1.1 Device Power-Management Architecture Building Blocks.................................................. 413
3.1.1.1 Clock Management........................................................................................ 413
3.1.1.1.1 Module Interface and Functional Clocks........................................................... 413
3.1.1.1.2 Module-Level Clock Management .................................................................. 414
3.1.1.1.3 Clock Domain.......................................................................................... 419
3.1.1.1.4 Clock Domain-Level Clock Management .......................................................... 420
3.1.1.1.5 Clock Domain HW_AUTO Mode Sequences ..................................................... 421
3.1.1.1.6 Clock Domain Sleep/Wake-up ...................................................................... 424
3.1.1.1.7 Clock Domain Dependency.......................................................................... 425
3.1.1.2 Power Management....................................................................................... 432
3.1.1.2.1 Power Domain......................................................................................... 432
3.1.1.2.2 Module Logic and Memory Context ................................................................ 434
3.1.1.2.3 Power Domain Management ........................................................................ 434
3.1.1.3 Voltage Management ..................................................................................... 436
3.1.1.3.1 Voltage Domain ....................................................................................... 436
3.1.1.3.2 Voltage Domain Management....................................................................... 437
3.1.1.3.3 AVS Overview ......................................................................................... 437
3.1.2 Power-Management Techniques .............................................................................. 439
3.1.2.1 Standby Leakage Management ......................................................................... 439
3.1.2.2 Dynamic Voltage and Frequency Scaling .............................................................. 440
3.1.2.3 Dynamic Power Switching................................................................................ 440
3.1.2.4 Adaptive Voltage Scaling................................................................................. 441
3.1.2.5 Adaptive Body Bias ....................................................................................... 441
3.1.2.6 SR3-APG (Automatic Power Gating) ................................................................... 442
3.1.2.7 Combining Power-Management Techniques .......................................................... 442
3.1.2.7.1 DPS Versus SLM ..................................................................................... 443
3.2 PRCM Subsystem Overview ............................................................................................ 444
3.2.1 Introduction ....................................................................................................... 444
3.2.2 Power-Management Framework Features ................................................................... 445
3.3 PRCM Subsystem Environment ........................................................................................ 447
3.3.1 External Clock Signals .......................................................................................... 447
3.3.2 External Boot Signals ........................................................................................... 447
3.3.3 External Reset Signals.......................................................................................... 448
3.3.4 External Voltage Inputs ......................................................................................... 449
3.4 PRCM Subsystem Integration........................................................................................... 450
3.4.1 Device Power-Management Layout ........................................................................... 450
3.4.2 Power-Management Scheme, Reset, and Interrupt Requests............................................. 454
3.4.2.1 Power Domain ............................................................................................. 454
3.4.2.2 Resets....................................................................................................... 454
3.4.2.3 PRCM Interrupt Requests ................................................................................ 454
3.5 Reset Management Functional Description ........................................................................... 456
3.5.1 Overview .......................................................................................................... 456
3.5.1.1 PRCM Reset Management Functional Description ................................................... 456
3.5.1.1.1 Power-On Reset ...................................................................................... 456
3.5.1.1.2 Warm Reset ........................................................................................... 456
3.5.1.2 PRM Reset Management Functional Description ..................................................... 456
3.5.2 General Characteristics of Reset Signals .................................................................... 456
3.5.2.1 Scope ....................................................................................................... 457
3.5.2.2 Occurrence ................................................................................................. 457
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3.5.2.3 Source Type................................................................................................ 457
3.5.2.4 Retention Type............................................................................................. 457
3.5.3 Reset Sources.................................................................................................... 458
3.5.3.1 Global Reset Sources..................................................................................... 458
3.5.3.2 Local Reset Sources ...................................................................................... 458
3.5.4 Reset Logging.................................................................................................... 459
3.5.5 Reset Domains................................................................................................... 459
3.5.6 Reset Sequences................................................................................................ 485
3.5.6.1 MPU Subsystem Power-On Reset Sequence ......................................................... 485
3.5.6.2 MPU Subsystem Warm Reset Sequence .............................................................. 486
3.5.6.3 MPU Subsystem Reset Sequence on Sleep and Wake-Up Transitions From RETENTION
State......................................................................................................... 486
3.5.6.4 IVA Subsystem Power-On Reset Sequence........................................................... 487
3.5.6.5 IVA Subsystem Software Warm Reset Sequence .................................................... 488
3.5.6.6 DSP1 Subsystem Power-On Reset Sequence ........................................................ 489
3.5.6.7 DSP1 Subsystem Software Warm Reset Sequence.................................................. 489
3.5.6.8 DSP2 Subsystem Power-On Reset Sequence ........................................................ 490
3.5.6.9 DSP2 Subsystem Software Warm Reset Sequence.................................................. 491
3.5.6.10 IPU1 Subsystem Power-On Reset Sequence ......................................................... 491
3.5.6.11 IPU1 Subsystem Software Warm Reset Sequence................................................... 492
3.5.6.12 IPU2 Subsystem Power-On Reset Sequence ......................................................... 493
3.5.6.13 IPU2 Subsystem Software Warm Reset Sequence................................................... 494
3.5.6.14 EVE1 Subsystem Power-On Reset Sequence ........................................................ 495
3.5.6.15 EVE1 Subsystem Software Warm Reset Sequence.................................................. 496
3.5.6.16 EVE2 Subsystem Power-On Reset Sequence ........................................................ 497
3.5.6.17 EVE2 Subsystem Software Warm Reset Sequence.................................................. 497
3.5.6.18 EVE3 Subsystem Power-On Reset Sequence ........................................................ 498
3.5.6.19 EVE3 Subsystem Software Warm Reset Sequence.................................................. 499
3.5.6.20 EVE4 Subsystem Power-On Reset Sequence ........................................................ 499
3.5.6.21 EVE4 Subsystem Software Warm Reset Sequence.................................................. 500
3.5.6.22 Global Warm Reset Sequence .......................................................................... 501
3.6 Clock Management Functional Description ........................................................................... 503
3.6.1 Overview .......................................................................................................... 503
3.6.2 External Clock Inputs............................................................................................ 504
3.6.2.1 FUNC_32K_CLK Clock .................................................................................. 504
3.6.2.2 High-Frequency System Clock Input.................................................................... 504
3.6.2.3 External Reference Clock Input ......................................................................... 504
3.6.3 Internal Clock Sources and Generators ...................................................................... 504
3.6.3.1 PRM Clock Source ........................................................................................ 504
3.6.3.2 CM Clock Source.......................................................................................... 506
3.6.3.2.1 CM_CORE_AON Clock Generator ................................................................. 506
3.6.3.2.2 CM_CORE_AON_CLKOUTMUX Overview ....................................................... 511
3.6.3.2.3 CM_CORE_AON_TIMER Overview ............................................................... 516
3.6.3.2.4 CM_CORE_AON_MCASP1 Overview ............................................................ 520
3.6.3.3 Generic DPLL Overview .................................................................................. 522
3.6.3.3.1 Generic APLL Overview.............................................................................. 523
3.6.3.3.2 DPLLs Output Clocks Parameters.................................................................. 524
3.6.3.3.3 Enable Control, Status, and Low-Power Operation Mode....................................... 526
3.6.3.3.4 DPLL Power Modes .................................................................................. 526
3.6.3.3.5 DPLL Recalibration ................................................................................... 528
3.6.3.3.6 DPLL Output Power Down........................................................................... 529
3.6.3.4 DPLL_PER Description................................................................................... 529
3.6.3.4.1 DPLL_PER Overview................................................................................. 529
3.6.3.4.2 DPLL_PER Synthesized Clock Parameters....................................................... 529
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Contents
3.6.3.4.3 DPLL_PER Power Modes ........................................................................... 530
3.6.3.4.4 DPLL_PER Recalibration ............................................................................ 530
3.6.3.5 DPLL_CORE Description................................................................................. 531
3.6.3.5.1 DPLL_CORE Overview .............................................................................. 531
3.6.3.5.2 DPLL_CORE Synthesized Clock Parameters..................................................... 532
3.6.3.5.3 DPLL_CORE Power Modes ......................................................................... 532
3.6.3.5.4 DPLL_CORE Recalibration.......................................................................... 533
3.6.3.6 DPLL_ABE Description ................................................................................... 533
3.6.3.6.1 DPLL_ABE Overview................................................................................. 533
3.6.3.6.2 DPLL_ABE Synthesized Clock Parameters ....................................................... 534
3.6.3.6.3 DPLL_ABE Power Modes ........................................................................... 534
3.6.3.6.4 DPLL_ABE Recalibration ............................................................................ 535
3.6.3.7 DPLL_MPU Description .................................................................................. 535
3.6.3.7.1 DPLL_MPU Overview ................................................................................ 535
3.6.3.7.2 DPLL_MPU Tactical Clocking Adjustment......................................................... 536
3.6.3.7.3 DPLL_MPU Synthesized Clock Parameters ...................................................... 536
3.6.3.7.4 DPLL_MPU Power Modes........................................................................... 536
3.6.3.7.5 DPLL_MPU Recalibration............................................................................ 537
3.6.3.8 DPLL_IVA Description .................................................................................... 537
3.6.3.8.1 DPLL_IVA Overview.................................................................................. 537
3.6.3.8.2 DPLL_IVA Synthesized Clock Parameters ........................................................ 538
3.6.3.8.3 DPLL_IVA Power Modes............................................................................. 538
3.6.3.8.4 DPLL_IVA Recalibration ............................................................................. 539
3.6.3.9 DPLL_USB Description................................................................................... 539
3.6.3.9.1 DPLL_USB Overview................................................................................. 539
3.6.3.9.2 DPLL_USB Synthesized Clock Parameters....................................................... 539
3.6.3.9.3 DPLL_USB Power Modes ........................................................................... 540
3.6.3.9.4 DPLL_USB Recalibration ............................................................................ 540
3.6.3.10 DPLL_EVE Description ................................................................................... 540
3.6.3.10.1 DPLL_EVE Overview................................................................................. 540
3.6.3.10.2 DPLL_EVE Synthesized Clock Parameters....................................................... 541
3.6.3.10.3 DPLL_EVE Power Modes ........................................................................... 541
3.6.3.10.4 DPLL_EVE Recalibration ............................................................................ 542
3.6.3.11 DPLL_DSP Description................................................................................... 542
3.6.3.11.1 DPLL_DSP Overview ................................................................................ 542
3.6.3.11.2 DPLL_DSP Synthesized Clock Parameters....................................................... 542
3.6.3.11.3 DPLL_DSP Power Modes ........................................................................... 543
3.6.3.11.4 DPLL_DSP Recalibration ............................................................................ 543
3.6.3.12 DPLL_GMAC Description ................................................................................ 544
3.6.3.12.1 DPLL_GMAC Overview.............................................................................. 544
3.6.3.12.2 DPLL_GMAC Synthesized Clock Parameters .................................................... 544
3.6.3.12.3 DPLL_GMAC Power Modes......................................................................... 545
3.6.3.12.4 DPLL_GMAC Recalibration ......................................................................... 545
3.6.3.13 DPLL_GPU Description................................................................................... 546
3.6.3.13.1 DPLL_GPU Overview ................................................................................ 546
3.6.3.13.2 DPLL_GPU Synthesized Clock Parameters ...................................................... 546
3.6.3.13.3 DPLL_GPU Power Modes........................................................................... 547
3.6.3.13.4 DPLL_GPU Recalibration............................................................................ 547
3.6.3.14 DPLL_DDR Description................................................................................... 548
3.6.3.14.1 DPLL_DDR Overview ................................................................................ 548
3.6.3.14.2 DPLL_DDR Synthesized Clock Parameters ...................................................... 548
3.6.3.14.3 DPLL_DDR Power Modes........................................................................... 548
3.6.3.14.4 DPLL_DDR Recalibration............................................................................ 549
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