Public Version
AM/DM37x Multimedia Device
Silicon Revision 1.x
Version R
Technical Reference Manual
Literature Number: SPRUGN4R
May 2010–Revised September 2012
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Public Version
Contents
Preface .................................................................................................................................... 170
1 Introduction .................................................................................................................... 183
1.1 Overview .................................................................................................................. 184
1.2 Environment .............................................................................................................. 186
1.3 Description ................................................................................................................ 187
1.3.1 MPU Subsystem ................................................................................................ 188
1.3.2 IVA2.2 Subsystem .............................................................................................. 188
1.3.3 On-Chip Memory ................................................................................................ 189
1.3.4 External Memory Interfaces ................................................................................... 189
1.3.5 DMA Controllers ................................................................................................. 190
1.3.6 Multimedia Accelerators ........................................................................................ 190
1.3.7 Comprehensive Power Management ......................................................................... 191
1.3.8 Peripherals ....................................................................................................... 191
1.4 Package-On-Package Concept ........................................................................................ 192
1.5 AM/DM37x Family ....................................................................................................... 195
1.5.1 Device Features ................................................................................................. 195
1.5.2 Device Identification ............................................................................................ 197
1.5.3 General Recommendations Relative to Unavailable Features/Modules ................................. 199
2 Memory Mapping ............................................................................................................. 200
2.1 Introduction ............................................................................................................... 201
2.2 Global Memory Space Mapping ....................................................................................... 203
2.3 L3 and L4 Memory Space Mapping ................................................................................... 206
2.3.1 L3 Memory Space Mapping ................................................................................... 206
2.3.2 L4 Memory Space Mapping ................................................................................... 207
2.3.2.1 L4-Core Memory Space Mapping ...................................................................... 207
2.3.2.2 L4-Wakeup Memory Space Mapping .................................................................. 210
2.3.2.3 L4-Peripheral Memory Space Mapping ................................................................ 211
2.3.2.4 L4-Emulation Memory Space Mapping ................................................................ 212
2.3.3 Register Access Restrictions .................................................................................. 213
2.4 IVA2.2 Subsystem Memory Space Mapping ......................................................................... 215
2.4.1 IVA2.2 Subsystem Internal Memory and Cache Allocation ............................................... 215
2.4.1.1 IVA2.2 Subsystem Memory Hierarchy ................................................................. 215
2.4.1.2 IVA2.2 Cache Allocation ................................................................................. 216
2.4.2 DSP Access to L2 Memories .................................................................................. 217
2.4.2.1 DSP Access to L2 ROM ................................................................................. 217
2.4.2.2 DSP Access to L2 RAM ................................................................................. 217
2.4.3 DSP and EDMA Access to Memories and Peripherals .................................................... 217
2.4.4 L3 Interconnect View of the IVA2.2 Subsystem Memory Space ......................................... 218
2.4.5 DSP View of the IVA2.2 Subsystem Memory Space ....................................................... 219
2.4.6 EDMA View of the IVA2.2 Subsystem Memory Space .................................................... 220
3 Power, Reset, and Clock Management ................................................................................ 222
3.1 Introduction to Power Managements .................................................................................. 223
3.1.1 Goal of Power Management ................................................................................... 223
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3.1.2 Power-Management Techniques ............................................................................. 223
3.1.2.1 Dynamic Voltage and Frequency Scaling ............................................................. 223
3.1.2.2 SmartReflex Adaptive Voltage Scaling (AVS) ........................................................ 224
3.1.2.3 Dynamic Power Switching ............................................................................... 225
3.1.2.4 Standby Leakage Management ......................................................................... 225
3.1.2.5 DPS Versus SLM ......................................................................................... 226
3.1.2.6 Adaptive Body Bias (ABB) ............................................................................... 226
3.1.2.7 Combining Power-Management Techniques ......................................................... 226
3.1.3 Architectural Blocks for Power Management ................................................................ 227
3.1.3.1 Clock Domain ............................................................................................. 227
3.1.3.2 Power Domain ............................................................................................ 228
3.1.3.3 Voltage Domain ........................................................................................... 229
3.1.4 Device Power-Management Architecture .................................................................... 230
3.1.4.1 Module Interface and Functional Clocks ............................................................... 231
3.1.4.2 Autoidle Clock Control ................................................................................... 232
3.1.5 SmartReflex Voltage-Control Overview ...................................................................... 233
3.1.5.1 Manual SmartReflex Voltage Control .................................................................. 234
3.1.5.2 Automatic SmartReflex Voltage Control ............................................................... 235
3.2 PRCM Overview ......................................................................................................... 236
3.2.1 Introduction ...................................................................................................... 236
3.2.2 PRCM Features ................................................................................................. 238
3.3 PRCM Environment ...................................................................................................... 239
3.3.1 External Clock Signals ......................................................................................... 240
3.3.2 External Reset Signals ......................................................................................... 241
3.3.3 External Power Signals ........................................................................................ 242
3.4 PRCM Integration ........................................................................................................ 243
3.4.1 Power-Management Scheme, Reset, and Interrupt Requests ............................................ 246
3.4.1.1 Power Domain ............................................................................................ 246
3.4.1.2 Resets ...................................................................................................... 246
3.4.1.3 Interrupt Requests ........................................................................................ 247
3.5 PRCM Functional Description .......................................................................................... 248
3.5.1 PRCM Reset Manager Functional Description .............................................................. 248
3.5.1.1 Overview ................................................................................................... 248
3.5.1.2 General Characteristics of Reset Signals ............................................................. 248
3.5.1.2.1 Scope .................................................................................................. 249
3.5.1.2.2 Occurrence ............................................................................................ 249
3.5.1.2.3 Source Type .......................................................................................... 249
3.5.1.3 Reset Sources ............................................................................................ 250
3.5.1.3.1 Global Reset Sources ............................................................................... 250
3.5.1.3.2 Local Reset Sources ................................................................................. 251
3.5.1.4 Reset Distribution ......................................................................................... 252
3.5.1.5 Power Domain Reset Descriptions ..................................................................... 253
3.5.1.5.1 MPU Power Domain ................................................................................. 253
3.5.1.5.2 NEON Power Domain ............................................................................... 254
3.5.1.5.3 IVA2 Power Domain ................................................................................. 254
3.5.1.5.4 CORE Power Domain ............................................................................... 254
3.5.1.5.5 DSS Power Domain .................................................................................. 254
3.5.1.5.6 CAM Power Domain ................................................................................. 255
3.5.1.5.7 USBHOST Power Domain .......................................................................... 255
3.5.1.5.8 SGX Power Domain ................................................................................. 255
3.5.1.5.9 WKUP Power Domain ............................................................................... 255
3.5.1.5.10 PER Power Domain ................................................................................. 255
3.5.1.5.11 SmartReflex Power Domain ........................................................................ 256
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3.5.1.5.12 DPLL Power Domains ............................................................................... 256
3.5.1.5.13 EFUSE Power Domain .............................................................................. 256
3.5.1.5.14 BANDGAP Logic ..................................................................................... 256
3.5.1.5.15 External Warm Reset Assertion .................................................................... 257
3.5.1.6 Reset Logging ............................................................................................. 257
3.5.1.6.1 PRCM Reset Logging Mechanism ................................................................. 257
3.5.1.6.2 SCM Reset Logging ................................................................................. 257
3.5.1.7 Reset Management Overview ........................................................................... 258
3.5.1.8 Reset Summary ........................................................................................... 263
3.5.1.9 Reset Sequences ......................................................................................... 266
3.5.1.9.1 Power-Up Sequence ................................................................................. 266
3.5.1.9.2 Global Warm Reset Sequence ..................................................................... 268
3.5.1.9.3 IVA2.2 Subsystem Power-Up Sequence .......................................................... 270
3.5.1.9.4 IVA2 Software Reset Sequence .................................................................... 272
3.5.1.9.5 IVA2 Global Warm Reset Sequence .............................................................. 274
3.5.1.9.6 IVA2 Power Domain Wake-Up Cold Reset Sequence .......................................... 276
3.5.2 PRCM Power Manager Functional Description ............................................................. 279
3.5.2.1 Overview ................................................................................................... 279
3.5.2.1.1 Introduction ............................................................................................ 279
3.5.2.1.2 Device Partitioning ................................................................................... 280
3.5.2.1.3 Memory and Logic Power Management .......................................................... 282
3.5.2.1.4 Retention Till Access (RTA) Memory Feature .................................................... 282
3.5.2.1.5 Power Domain States ............................................................................... 283
3.5.2.1.6 Power State Transitions ............................................................................. 283
3.5.2.1.7 Device Power Modes ................................................................................ 284
3.5.2.1.8 Isolation Between Power Domains ................................................................ 284
3.5.2.2 Power Domain Implementation ......................................................................... 284
3.5.2.2.1 Device Power Domains .............................................................................. 284
3.5.2.2.2 Power Domain Memory Status ..................................................................... 286
3.5.2.2.3 Power Domain State Transition Rules ............................................................ 286
3.5.2.2.4 Power Domain Dependencies ...................................................................... 286
3.5.2.2.5 Power Domain Controls ............................................................................. 287
3.5.3 PRCM Clock Manager Functional Description .............................................................. 289
3.5.3.1 Overview ................................................................................................... 289
3.5.3.1.1 Interface and Functional Clocks .................................................................... 290
3.5.3.2 External Clock I/Os ....................................................................................... 291
3.5.3.2.1 External Clock Inputs ................................................................................ 291
3.5.3.2.2 External Clock Outputs .............................................................................. 292
3.5.3.2.3 Summary .............................................................................................. 292
3.5.3.3 Internal Clock Generation ............................................................................... 292
3.5.3.3.1 PRM .................................................................................................... 294
3.5.3.3.2 CM ..................................................................................................... 296
3.5.3.3.3 DPLLs .................................................................................................. 298
3.5.3.3.4 DPLL Clock Summary ............................................................................... 306
3.5.3.3.5 Summary .............................................................................................. 306
3.5.3.4 Clock Distribution ......................................................................................... 307
3.5.3.4.1 Power Domain Clock Distribution .................................................................. 307
3.5.3.4.2 Clock Distribution Summary ........................................................................ 321
3.5.3.5 External Clock Controls .................................................................................. 323
3.5.3.5.1 Clock Request (sys_clkreq) Control ............................................................... 323
3.5.3.5.2 System Clock Oscillator Control .................................................................... 324
3.5.3.5.3 External Output Clock1 (sys_clkout1) Control .................................................... 327
3.5.3.5.4 External Output Clock2 (sys_clkout2) Control .................................................... 327
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SPRUGN4R–May 2010–Revised September 2012 Contents
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