【免费】32Meg x 8, 16Meg x16 256Mb SYNCHRONOUS DRAM手册资源-CSDN文库

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IS42S83200G, IS42S16160G

IS45S83200G, IS45S16160G

Integrated Silicon Solution, Inc. — www.issi.com 1

Rev. A

3/20/2012

out notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to obtain

the latest version of this device speciﬁcation before relying on any published information and before placing orders for products.

Integrated Silicon Solution, Inc. does not recommend the use of any of its products in life support applications where the failure or malfunction of the product can

reasonably be expected to cause failure of the life support system or to signiﬁcantly affect its safety or effectiveness. Products are not authorized for use in such ap-

plications unless Integrated Silicon Solution, Inc. receives written assurance to its satisfaction, that:

a.) the risk of injury or damage has been minimized;

b.) the user assume all such risks; and

c.) potential liability of Integrated Silicon Solution, Inc is adequately protected under the circumstances

FEATURES

• Clock frequency: 166, 143 MHz

• Fully synchronous; all signals referenced to a

positive clock edge

• Internal bank for hiding row access/precharge

• Single Power supply: 3.3V + 0.3V

• LVTTL interface

• Programmable burst length

– (1, 2, 4, 8, full page)

• Programmable burst sequence:

Sequential/Interleave

• Auto Refresh (CBR)

• Self Refresh

• 8K refresh cycles every 32 ms (A2 grade) or

64 ms (commercial, industrial, A1 grade)

• Random column address every clock cycle

• Programmable CAS latency (2, 3 clocks)

• Burst read/write and burst read/single write

operations capability

• Burst termination by burst stop and precharge

command

OPTIONS

• Package:

54-pin TSOP-II

54-ball BGA

• Operating Temperature Range:

Commercial (0

C to +70

Industrial (-40

C to +85

Automotive Grade A1 (-40

C to +85

Automotive Grade A2 (-40

C to +105

OVERVIEW

ISSI's 256Mb Synchronous DRAM achieves high-speed

data transfer using pipeline architecture. All inputs and

outputs signals refer to the rising edge of the clock input.

The 256Mb SDRAM is organized as follows.

32Meg x 8, 16Meg x16

256Mb SYNCHRONOUS DRAM

MARCH 2012

IS42S83200G IS42S16160G

8M x 8 x 4 Banks 4M x16x4 Banks

54-pin TSOPII 54-pin TSOPII

54-ball BGA 54-ball BGA

Parameter 32M x 8 16M x 16

Conguration 8M x 8 x 4

banks

4M x 16 x 4

banks

Refresh Count

Com./Ind.

8K/64ms

8K/16ms

8K/64ms

8K/16ms

Row Addresses A0-A12 A0-A12

Column Addresses A0-A9 A0-A8

Bank Address Pins BA0, BA1 BA0, BA1

Auto Precharge Pins A10/AP A10/AP

ADDRESS TABLE

KEY TIMING PARAMETERS

Parameter -6 -7 Unit

Clk Cycle Time

CAS Latency = 3 6 7 ns

CAS Latency = 2 10 7.5 ns

Clk Frequency

CAS Latency = 3 166 143 Mhz

CAS Latency = 2 100 133 Mhz

Access Time from Clock

CAS Latency = 3 5.4 5.4 ns

CAS Latency = 2 6.5 5.4 ns

2 Integrated Silicon Solution, Inc. — www.issi.com

Rev. A

3/20/2012

IS42S83200G, IS42S16160G

IS45S83200G, IS45S16160G

DEVICE OVERVIEW

The 256Mb SDRAM is a high speed CMOS, dynamic

random-access memory designed to operate in 3.3V Vdd

and 3.3V Vddq memory systems containing 268,435,456

bits. Internally conﬁgured as a quad-bank DRAM with a

synchronous interface. Each 67,108,864-bit bank is orga-

nized as 8,192 rows by 512 columns by 16 bits or 8,192

rows by 1,024 columns by 8 bits.

The 256Mb SDRAM includes an AUTO REFRESH MODE,

and a power-saving, power-down mode. All signals are

registered on the positive edge of the clock signal, CLK.

All inputs and outputs are LVTTL compatible.

The 256Mb SDRAM has the ability to synchronously burst

data at a high data rate with automatic column-address

generation, the ability to interleave between internal banks

to hide precharge time and the capability to randomly

change column addresses on each clock cycle during

burst access.

A self-timed row precharge initiated at the end of the burst

sequence is available with the AUTO PRECHARGE function

enabled.

Precharge

one bank while accessing one of the

other three banks will hide the

precharge

cycles and provide

seamless, high-speed, random-access operation.

SDRAM

read and write accesses are burst oriented starting

at a selected location and continuing for a programmed

number of locations in a programmed sequence. The

registration of an ACTIVE command begins accesses,

followed by a READ or WRITE command. The ACTIVE

command in conjunction with address bits registered are

used to select the bank and row to be accessed (BA0,

BA1 select the bank; A0-A12 select the row). The READ

or WRITE commands in conjunction with address bits

registered are used to select the starting column location

for the burst access.

Programmable READ or WRITE burst lengths consist of

1, 2, 4 and 8 locations or full page, with a burst terminate

option.

CLK

CKE

RAS

CAS

BA0

BA1

A10

A12

COMMAND

DECODER

CLOCK

GENERATOR

MODE

REFRESH

CONTROLLER

REFRESH

COUNTER

SELF

REFRESH

CONTROLLER

ROW

ADDRESS

LATCH

MULTIPLEXER

COLUMN

ADDRESS LATCH

BURST COUNTER

COLUMN

ADDRESS BUFFER

COLUMN DECODER

DATA IN

BUFFER

DATA OUT

BUFFER

DQML

DQMH

DQ 0-15

DDQ

16 16

512

(x 16)

8192

ROW DECODER

8192

MEMORY CELL

ARRAY

BANK 0

SENSE AMP I/O GATE

BANK CONTROL LOGIC

ROW

ADDRESS

BUFFER

A11

FUNCTIONAL BLOCK DIAGRAM (FOR 4Mx16x4 BANKS SHOWN)

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