JEDEC Standard No. 22-A117C
Page 1
ELECTRICALLY ERASABLE PROGRAMMABLE ROM (EEPROM)
PROGRAM/ERASE ENDURANCE AND DATA RETENTION STRESS TEST
(From
JEDEC Board Ballot JCB-11-7x, formulated under the cognizance of the JC-14.1 Subcommittee
on Reliability Test Method and Packaged Devices.)
1 Scope
This stress test is intended to determine the ability of an EEPROM integrated circuit or an integrated
circuit with an EEPROM module (such as a microprocessor) to sustain repeated data changes without
failure (program/erase endurance) and to retain data for the expected life of the EEPROM (data retention).
This Standard specifies the procedural requirements for performing valid endurance and retention tests
based on a qualification specification. Endurance and retention qualification specifications (for cycle
counts, durations, temperatures, and sample sizes) are specified in JESD47 or may be developed using
knowledge-based methods as in JESD94.
This stress test does not replace other stress test qualification requirements. The program/erase endurance
and data retention test for qualification and monitoring, using the parameter levels specified in JESD47, is
considered destructive. Lesser test parameter levels (e.g., of temperature, number of cycles, retention
bake duration) may be used for screening as long as these parameter levels have been verified by the
device manufacturer to be nondestructive; this can be performed anywhere from wafer level to finished
device.
2 Terms and definitions
2.1 EEPROM
A reprogrammable read-only memory in which the cells at each address can be erased electrically and
reprogrammed electrically.
NOTE The term EEPROM in this document includes all such memories, including FLASH EEPROM integrated
circuits and embedded memory in integrated circuits such as Erasable Programmable Logic Devices (EPLDs) and
microcontrollers. Destructive-read memories such as ferroelectric memories, in which the read operation re-writes
the data in the memory cells, are beyond the scope of this document.
2.2 Data pattern
The mix of 1s and 0s in the memory and their physical or logical positions.
NOTE A device may be single-bit-per-cell (SBC), meaning that one physical memory cell stores a “0” or a “1”, or
multiple-bits-per-cell (MBC), meaning that one cell stores typically two bits of data: “00”, “01”, “10”, or “11”. In
some MBC memories, the two bits represent logically-adjacent bit-pairs in each byte of data. For example, a byte
containing binary data 10110001 would correspond to four physical cells with data 2301 in base-four logic. In
other MBC memories, the two bits may represent bits in entirely different address locations. For an SBC memory a
physical checkerboard pattern consists of alternating 0s and 1s, with each 0 surrounded by 1s on either side and
above and below; a logical checkerboard pattern consists of data bytes AAH or 55H in which each 0 is logically
adjacent to 1s. In some qualifications only logical positions may be known.
Test Method A117C
(Revision of Test Method A117B)
