Gen3 Integrated Block for PCIe v4.3 4
PG023 October 4, 2017 www.xilinx.com Product Specification
Introduction
The Virtex
®
-7 FPGA Gen3 Integrated Block for
PCI Express
®
core is a high-bandwidth,
scalable, and reliable serial interconnect
building block solution for use with all Virtex-7
XT and HT FPGAs except the XC7VX485T. The
Integrated Block for PCI Express (PCIe
®
)
solution supports 1-lane, 2-lane, 4-lane, and
8-lane Endpoint configurations, including Gen1
(2.5 GT/s), Gen2 (5.0 GT/s) and Gen3 (8 GT/s)
speeds. It is compliant with PCI Express Base
Specification, rev. 3.0 [Ref 2]. This solution
supports the AXI4-Stream interface for the
customer user interface.
PCI Express offers a serial architecture that
alleviates many limitations of parallel bus
architectures by using clock data recovery
(CDR) and differential signaling. Using CDR (as
opposed to source synchronous clocking)
lowers pin count, enables superior frequency
scalability, and makes data synchronization
easier. PCI Express technology, adopted by the
PCI-SIG
®
as the next generation PCI™, is
backward-compatible to the existing PCI
software model.
With higher bandwidth per pin, low overhead,
low latency, reduced signal integrity issues, and
CDR architecture, the integrated block sets the
industry standard for a high-performance,
cost-efficient PCIe solution.
The Virtex-7 Gen3 Integrated Block for PCIe
solution is compatible with industry-standard
application form factors such as the PCI Express
Card Electromechanical (CEM) v3.0 and the PCI
Industrial Computer Manufacturers Group
(PICMG) v3.4 specifications [Ref 2].
For a list of features, see Feature Summary.
IP Facts
LogiCORE™ IP Facts Table
Core Specifics
Supported
Device
Family
(1)
Virtex-7 XT and HT
(2)
Supported
User Interfaces
AXI4-Stream
Resources Resource Utilization
Provided with Core
Design Files Verilog
Example
Design
Verilog
Test Bench Verilog
Constraints
File
XDC
Simulation
Model
Verilog
Supported
S/W Drivers
N/A
Tested Design Flows
(3)
Design Entry Vivado® Design Suite
Simulation
For a list of supported simulators, see the
Xilinx Design Tools: Release Notes Guide
Synthesis Vivado synthesis
Support
Provided by Xilinx at the Xilinx Support web page
Notes:
1. For a complete listing of supported devices, see the Vivado IP
catalog.
2. Except for the XC7VX485T, XC7V585T and XC7V2000T.
3. For the supported versions of the tools, see the
Xilinx Design Tools: Release Notes Guide
.
