Document Number: 544905, Revision: 1.0 Intel Confidential 5
Figures
Figure 3-1 Definition of Hysteresis ...................................................................................17
Figure 3-2 Measurement Points for VCLK high, low, rise, and fall time, Tperiod .....................19
Figure 3-3 Serial VID Bit Transfer Concept ........................................................................19
Figure 3-4 Clock/Data Sample CPU Driving Timing Definitions .............................................20
Figure 3-5 Clock/Data Sample VR Driving Timing Definitions (all segments) .........................20
Figure 3-6 Typical SVID Daisy Chain Topologies ................................................................22
Figure 3-7 Dynamic VID Avershoot Allowance ...................................................................36
Figure 3-8 VR settled, T_Alert from Low to High, from PS0, PS1, PS2 ..................................36
Figure 3-9 VR settled, T_Alert Starting from PS3 with SetVID Command ..............................37
Figure 3-10 VID Down VR_Settled and T_Alert ....................................................................38
Figure 3-11 Example of Efficiency Targets in Various Power States ........................................39
Figure 3-12 IMON Averaging Limits including: sample, register update delays ........................43
Figure 3-13 CPU Domain Input Power Sensor Concept .........................................................47
Figure 3-14 Memory Domain Input Power Sensor Concept ....................................................47
Figure 4-1 Typical VR Startup Timings..............................................................................51
Figure 4-2 VR Enable Deassertion Timings ........................................................................53
Figure 6-1 Thermal Zone and Detection Encoding (required servers, optional client) ..............57
Figure 6-2 VR_Hot#, SVID Thermal Alert without Thermal Zone Register support ..................58
Figure 6-3 VR_Hot#, SVID Thermal Alert for PWM ICs that Support Thermal Zone ................58
Figure 6-4 VR Tolerance Definitions (neglecting overshoot relief).........................................61
Tables
Table 1-1 Feature Support Terminology ........................................................................... 7
Table 1-2 Glossary ........................................................................................................ 7
Table 2-1 Mainstream Server, Microserver & Xeon Phi Market Segments VR13.0 Parameters .11
Table 2-2 Required Serial VID Registers and Functions .....................................................13
Table 3-1 VR DC Electrical Parameters ............................................................................17
Table 3-2 VR AC Electrical Parameters ............................................................................18
Table 3-3 VCLK AC Timing Parameters ............................................................................18
Table 3-4 Address Definitions per Socket ........................................................................23
Table 3-5 Input Sensors Locations on Xeon Memory VR’s ..................................................24
Table 3-6 VR13.0 VID Range and Power State Support .....................................................24
Table 3-7 VID Table ......................................................................................................25
Table 3-8 Overshoot Durations ......................................................................................35
Table 3-9 Preliminary Vboot Voltage Levels .....................................................................41
Table 3-10 IMON Averaging Rates ....................................................................................42
Table 3-11 IMON Accuracy Targets, 5% DCR inductors, 1% NTC ..........................................45
Table 3-12 IMON Accuracy Targets, 7% DCR inductors, 3% NTC ..........................................45
Table 3-13 IMON Accuracy Targets, MOSFET Power Stage Sensing .......................................46
Table 3-14 Work Point Voltage Mapping examples ..............................................................49
Table 4-1 VR Startup and Enable Timings ........................................................................51
Table 4-2 Enable Pin Voltage Levels ................................................................................53
Table 6-1 Open Drain Output Signal Specifications (VR_Ready)..........................................56
Table 6-2 Input Voltage by Segment ..............................................................................62
Table 8-1 Minimum Recommended PMBus Command Set ..................................................65
