################################################################################
# Vivado (TM) v2018.3 (64-bit)
#
# README.txt: Please read the sections below to understand the steps required
# to simulate the design for a simulator, the directory structure
# and the generated exported files.
#
################################################################################
1. Simulate Design
To simulate design, cd to the simulator directory and execute the script.
For example:-
% cd questa
% ./top.sh
The export simulation flow requires the Xilinx pre-compiled simulation library
components for the target simulator. These components are referred using the
'-lib_map_path' switch. If this switch is specified, then the export simulation
will automatically set this library path in the generated script and update,
copy the simulator setup file(s) in the exported directory.
If '-lib_map_path' is not specified, then the pre-compiled simulation library
information will not be included in the exported scripts and that may cause
simulation errors when running this script. Alternatively, you can provide the
library information using this switch while executing the generated script.
For example:-
% ./top.sh -lib_map_path /design/questa/clibs
Please refer to the generated script header 'Prerequisite' section for more details.
2. Directory Structure
By default, if the -directory switch is not specified, export_simulation will
create the following directory structure:-
<current_working_directory>/export_sim/<simulator>
For example, if the current working directory is /tmp/test, export_simulation
will create the following directory path:-
/tmp/test/export_sim/questa
If -directory switch is specified, export_simulation will create a simulator
sub-directory under the specified directory path.
For example, 'export_simulation -directory /tmp/test/my_test_area/func_sim'
command will create the following directory:-
/tmp/test/my_test_area/func_sim/questa
By default, if -simulator is not specified, export_simulation will create a
simulator sub-directory for each simulator and export the files for each simulator
in this sub-directory respectively.
IMPORTANT: Please note that the simulation library path must be specified manually
in the generated script for the respective simulator. Please refer to the generated
script header 'Prerequisite' section for more details.
3. Exported script and files
Export simulation will create the driver shell script, setup files and copy the
design sources in the output directory path.
By default, when the -script_name switch is not specified, export_simulation will
create the following script name:-
<simulation_top>.sh (Unix)
When exporting the files for an IP using the -of_objects switch, export_simulation
will create the following script name:-
<ip-name>.sh (Unix)
Export simulation will create the setup files for the target simulator specified
with the -simulator switch.
For example, if the target simulator is "ies", export_simulation will create the
'cds.lib', 'hdl.var' and design library diectories and mappings in the 'cds.lib'
file.
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CIC插值滤波器的FPGA实现
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CIC插值滤波器的FPGA实现 (559个子文件)
__synthesis_is_complete__ 0B
__synthesis_is_complete__ 0B
__synthesis_is_complete__ 0B
__synthesis_is_complete__ 0B
__synthesis_is_complete__ 0B
__synthesis_is_complete__ 0B
__synthesis_is_complete__ 0B
runme.bat 229B
runme.bat 229B
runme.bat 229B
runme.bat 229B
runme.bat 229B
runme.bat 229B
runme.bat 229B
runme.bat 229B
design_1.bd 9KB
design_1_wrapper.bit 3.86MB
design_1.bxml 6KB
design_1_wrapper_routed.dcp 4.5MB
design_1_wrapper_placed.dcp 3.92MB
design_1_wrapper_opt.dcp 2.7MB
design_1_ila_0_0.dcp 677KB
design_1_ila_0_2.dcp 676KB
design_1_ila_0_2.dcp 676KB
design_1_ila_0_1.dcp 676KB
design_1_ila_0_1.dcp 676KB
design_1_ila_0_0.dcp 676KB
design_1_ila_0_2.dcp 676KB
design_1_ila_0_1.dcp 676KB
design_1_ila_0_0.dcp 602KB
dbg_hub.dcp 372KB
dbg_hub.dcp 365KB
dbg_hub.dcp 357KB
dbg_hub.dcp 347KB
design_1_vio_0_0.dcp 127KB
design_1_vio_0_0.dcp 127KB
design_1_vio_0_0.dcp 126KB
design_1_dds_compiler_0_0.dcp 113KB
design_1_dds_compiler_0_0.dcp 113KB
design_1_dds_compiler_0_0.dcp 112KB
design_1_clc_0_0.dcp 65KB
design_1_clc_0_0.dcp 65KB
design_1_wrapper.dcp 13KB
design_1_clk_wiz_0_0.dcp 10KB
design_1_clk_wiz_0_0.dcp 10KB
design_1_clk_wiz_0_0.dcp 10KB
design_1_clk_wiz_0_0.dcp 10KB
design_1_clk_wiz_0_0.dcp 9KB
compile.do 3KB
compile.do 3KB
compile.do 3KB
compile.do 3KB
simulate.do 330B
simulate.do 324B
simulate.do 324B
elaborate.do 202B
simulate.do 193B
wave.do 32B
wave.do 32B
wave.do 32B
wave.do 32B
simulate.do 11B
run.f 1KB
run.f 1KB
design_1_xlconstant_0_0.h 3KB
design_1_xlconstant_0_0.h 3KB
design_1_xlconstant_0_0.h 3KB
design_1_xlconstant_0_0.h 3KB
design_1_xlconstant_0_0.h 3KB
design_1_xlconstant_0_0.h 3KB
design_1_xlconstant_0_0.h 3KB
design_1_xlconstant_0_0.h 3KB
design_1_xlconstant_0_0.h 3KB
design_1_xlconstant_0_0.h 3KB
design_1_xlconstant_0_0.h 3KB
design_1_xlconstant_0_1.h 3KB
xlconstant_v1_1_5.h 3KB
xlconstant_v1_1_5.h 3KB
xlconstant_v1_1_5.h 3KB
xlconstant_v1_1_5.h 3KB
xlconstant_v1_1_5.h 3KB
xlconstant_v1_1_5.h 3KB
xlconstant_v1_1_5.h 3KB
xlconstant_v1_1_5.h 3KB
xlconstant_v1_1_5.h 3KB
xlconstant_v1_1_5.h 3KB
xlconstant_v1_1_5.h 3KB
xlconstant_v1_1_5.h 3KB
design_1_wrapper.hdf 226KB
usage_statistics_webtalk.html 427KB
design_1_wrapper.hwdef 46KB
design_1.hwdef 46KB
design_1.hwh 616KB
hw_ila_data_1.ila 47KB
hw_ila_data_2.ila 37KB
hw_ila_data_3.ila 29KB
xsim.ini 22KB
vivado.jou 888B
vivado.jou 853B
vivado.jou 825B
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