module RxControl(
input clock,
input clk2M,
input clk960K,
input reset,
input RxCHRegEn,
input RxRegisterEn,
input [3:0]DSPSignal,
input [31:0]InAED,
input [31:0]TxRAMq,
input inA,
input inB,
output reg [31:0]RxReceiveData,
output reg [7:0]RxWriteAddress,
output reg RxRAMwrreq,
output wire [31:0]OutAED,
output reg [7:0]RxReadAddress
);
reg clk1M,clk250K,clk240K,clk125K,clk120K,clk500K,clk480K;
reg RxModuleClk;
reg [31:0]RxDataReg,RxControlReg;
reg ReceiveDataState;
reg [8:0]RxRAMdws;
reg [2:0]RxRAMStatus;
reg WriteS,ReadS,RxRAMrdreq;
wire sig,readFlag,WriteRAMFlag;
reg [31:0]RxData;
reg RxDataOk,ParityOK,ReceiveReply;
reg [5:0]BitCount;
reg ParityValue,BitesJudge;
reg BitesJGErr,DataBitError;
reg NewDataflag,FBStart,ShiftFlag;
reg [7:0]FBCount;
reg AFlag,BFlag,NFlag;
reg ASignalErr,BSignalErr,NSignalErr;
reg [3:0]Acount,Bcount;
reg [4:0]Ncount;
reg AStart,BStart,NStart;
reg CompareOver,WriteDataFinish;
reg SDICompareErr;
/************************Rx clock module**************/
always @(posedge clk2M or negedge reset)
begin
if(!reset) clk1M<=0;
else clk1M<=~clk1M;
end
always @(posedge clk1M or negedge reset)
begin
if(!reset) clk500K<=0;
else clk500K<=~clk500K;
end
always @(posedge clk960K or negedge reset)
begin
if(!reset) clk480K<=0;
else clk480K<=~clk480K;
end
always @(posedge clk500K or negedge reset)
begin
if(!reset) clk250K<=0;
else clk250K<=~clk250K;
end
always @(posedge clk250K or negedge reset)
begin
if(!reset) clk125K<=0;
else clk125K<=~clk125K;
end
always @(posedge clk480K or negedge reset)
begin
if(!reset) begin
clk120K<=0;
clk240K<=0;
end
else if(clk240K) begin
clk120K<=~clk120K;
clk240K<=~clk240K;
end
else clk240K<=~clk240K;
end
always @(RxControlReg or clk2M or clk1M or clk960K or clk250K or clk125K or clk120K)
begin
case (RxControlReg[5:4])
2'b00: begin
if(RxControlReg[14]) RxModuleClk=clk250K;
else RxModuleClk=clk2M;
end
2'b01: begin
if(RxControlReg[14]) RxModuleClk=clk125K;
else RxModuleClk=clk1M;
end
2'b10: begin
if(RxControlReg[14]) RxModuleClk=clk120K;
else RxModuleClk=clk960K;
end
default: RxModuleClk=0;
endcase
end
/*********************Register read or write************************/
assign sig=RxCHRegEn & DSPSignal[2];
assign OutAED= sig ? (RxRegisterEn ? TxRAMq : RxControlReg) : 32'hzzzzzzzz;
always @(posedge clock or negedge reset)
begin
if(!reset) RxControlReg<=0;
else if( !RxRegisterEn & RxCHRegEn & DSPSignal[3] ) RxControlReg<={InAED[31:3],RxRAMStatus[2:0]};
else RxControlReg[2:0]<=RxRAMStatus[2:0];
end
always @(posedge clock or negedge reset)
begin
if(!reset) RxRAMrdreq<=0;
else if(RxRegisterEn && RxCHRegEn && DSPSignal[2]) RxRAMrdreq<=1;
else RxRAMrdreq<=0;
end
always @(posedge clock or negedge reset)
begin
if(!reset) begin
RxReadAddress<=0;
RxWriteAddress<=0;
RxRAMdws<=0;
WriteS<=0;
ReadS<=0;
end
else if(!RxControlReg[3]) begin
RxReadAddress<=0;
RxWriteAddress<=0;
RxRAMdws<=0;
WriteS<=0;
ReadS<=0;
end
else if(!RxRAMrdreq && ReadS && RxRAMStatus) begin
RxRAMdws<=RxRAMdws-1'b1;
RxReadAddress<=RxReadAddress+1'b1;
ReadS<=0;
end
else if(RxRAMrdreq && !ReadS && RxRAMStatus) ReadS<=1;
else if(!RxRAMwrreq & WriteS) begin
RxRAMdws<=RxRAMdws+1'b1;
RxWriteAddress<=RxWriteAddress+1'b1;
WriteS<=0;
end
else if(RxRAMwrreq & !WriteS) WriteS<=1;
end
always @(posedge clock or negedge reset)
begin
if(!reset) RxRAMStatus<=0;
else if(!RxControlReg[3]) RxRAMStatus<=0;
else begin
if(RxRAMdws>0) RxRAMStatus[0]<=1;
else RxRAMStatus[0]<=0;
if(RxRAMdws==256) RxRAMStatus[1]<=1;
else RxRAMStatus[1]<=0;
if(RxRAMdws>16) RxRAMStatus[2]<=1;
else RxRAMStatus[2]<=0;
end
end
/**************************Receive A B signal data**********************************/
always @(posedge RxModuleClk or negedge reset)
begin
if(!reset) begin
RxDataReg<=0;
ParityOK<=0;
end
else if(NSignalErr | !RxControlReg[3]) begin
RxDataReg<=0;
ParityOK<=0;
end
else if(ParityOK) ParityOK<=0;
else if( (BitCount==32) && !RxControlReg[12] ) begin
if(RxControlReg[15]) RxDataReg<=RxData;
else if(!RxControlReg[15]) begin
RxDataReg[31:0]<={RxData[28:8],RxData[30:29],RxData[31],RxData[0],RxData[1],
RxData[2],RxData[3],RxData[4],RxData[5],RxData[6],RxData[7]};
end
ParityOK<=1;
end
else if( (BitCount==32) && RxControlReg[12] ) begin
ParityOK<=1;//begin
if(RxControlReg[15]) RxDataReg[31:0]<={!ParityValue,RxData[30:0]};
else if(!RxControlReg[15]) begin
RxDataReg[31:0]<={ RxData[28:8],RxData[30:29],!ParityValue,
RxData[0],RxData[1],RxData[2],RxData[3],RxData[4],RxData[5],RxData[6],RxData[7] };
end
end
else if(BitesJGErr) RxDataReg<=0;
end
always @(posedge RxModuleClk or negedge reset)
begin
if(!reset) ReceiveDataState<=0;
else if( ((BitCount==32) && ReceiveDataState) || DataBitError || !RxControlReg[3] ) ReceiveDataState<=0;
else if((inA | inB) & !ReceiveDataState & RxControlReg[3]) ReceiveDataState<=1;
end
always @(posedge RxModuleClk or negedge reset)
begin
if(!reset) begin
RxDataOk<=0;
BitesJGErr<=0;
end
else if(DataBitError | !RxControlReg[3]) begin
BitesJGErr<=0;
RxDataOk<=0;
end
else if(RxDataOk) RxDataOk<=0;
else if(BitesJGErr) BitesJGErr<=0;
else if(ReceiveDataState & RxControlReg[3] & FBStart) begin
if(FBCount<72) BitesJGErr<=1;
else RxDataOk<=1;
end
else if(FBStart && (FBCount>95)) RxDataOk<=1;
end
//receive bit shift
always @(posedge RxModuleClk or negedge reset)
begin
if(!reset) begin
BitCount<=0;
RxData<=0;
ShiftFlag<=0;
DataBitError<=0;
end
else if(!RxControlReg[3]) begin
BitCount<=0;
RxData<=0;
ShiftFlag<=0;
DataBitError<=0;
end
else if(ASignalErr | BSignalErr | NSignalErr ) begin
RxData<=0;
BitCount<=0;
ShiftFlag<=0;
DataBitError<=1'b1;
end
else if(DataBitError) DataBitError<=0;
else if(ShiftFlag) ShiftFlag<=0;
else if(AFlag) begin
RxData[BitCount]<=1'b1;
BitCount<=BitCount+1'b1;
ShiftFlag<=1;
end
else if(BFlag) begin
RxData[BitCount]<=0;
BitCount<=BitCount+1'b1;
ShiftFlag<=1'b1;
end
else if(ParityOK) begin
BitCount<=0;
RxData<=0;
end
end
always @(posedge RxModuleClk or negedge reset) //bit 1
begin
if(!reset) begin
Acount<=0;
AFlag<=0;
AStart<=0;
ASignalErr<=0;
ParityValue<=0;
end
else if(DataBitError | !RxControlReg[3]) begin
AFlag<=0; ASignalErr<=0;
AStart<=0; Acount<=0;
ParityValue<=0;
end
else if(ShiftFlag) begin AFlag<=0; ASignalErr<=0; end
else if(ParityOK) ParityValue<=0;
else if(!inA & !inB & ReceiveDataState & AStart) begin
Acount<=0;
AStart<=0;
if( (Acount>4) && (Acount<17) ) begin
AFlag<=1'b1;
ParityValue<=ParityValue+1'b1;
end
else begin
ASignalErr<=1'b1;
ParityValue<=0;
end
end
else if(inA & !inB & ReceiveDataState) begin
Acount<=Acount+1'b1;
AStart<=1'b1;
end
end
always @(posedge RxModuleClk or negedge reset) //bit 0
begin
if(!reset) begin
Bcount<=0;
BFlag<=0;
BStart<=0;
BSignalErr<=0;
end
else if(DataBitError | !RxControlReg[3]) begin
BFlag<=0; BSignalErr<=0;
Bcount<=0; BStart<=0;
end
else if(ShiftFlag) begin BFlag<=0; BSignalErr<=0; end
else if(!inA & !inB & ReceiveDataState & BStart) begin
Bcount<=0;
BStart<=0;
if( (Bcount>4) && (Bcount<17) ) BFlag<=1'b1;
else BSignalErr<=1;
end
else if(!inA & inB & ReceiveDataState) begin
429FGPA.rar （2个子文件） 
429RX.txt 10KB 429TX.txt 6KB
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