SelectIO Interface Wizard v5.1 www.xilinx.com 4
PG070 October 5, 2016 Product Specification
Introduction
The LogiCORE™ IP SelectIO™ Interface Wizard
simplifies the integration of SelectIO
technology into system designs for supported
devices. The SelectIO Wizard creates an VHDL/
Verilog HDL wrapper file that instantiates and
configures I/O logic such as Input SERDES,
Output SERDES and DELAY blocks to customer
requirements. Additionally, it instantiates and
configures the desired I/O clock primitive,
connecting it to the instantiated I/O logic.
Features
• Supports input, output or bidirectional
buses, and data buses up to 16 bits wide
• Creates clock circuitry required to drive I/O
logic
• Optional data serialization support for each
FPGA family
• Optional data and/or clock delay insertion
• Single and double data rates
• Predefined templates support multiple data
bus standards: Chip-to-Chip, Camera
receiver, Camera transmitter, digital visual
interface (DVI) receiver, DVI transmitter and
serial gigabit media independent interface
(SGMII)
• Output from the SelectIO Wizard can be
imported into the I/O planning project for
further I/O attribute modifications
• Provides synthesizable example design and
demonstration test bench to help with
integration
IP Facts
LogiCORE IP Facts Table
Core Specifics
Supported
Device Family
(1)
Zynq®-7000, Artix®-7, Virtex®-7, Kintex®-7
Supported User
Interfaces
Native
Resource
Utilization
Not Applicable
Provided with Core
Design Files Verilog
Example Design Verilog
Test Bench Verilog
Constraints File Xilinx Design Constraints (XDC)
Simulation
Model
None
Supported
S/W Driver
N/A
Tested Design Flows
(2)
Design Entry Vivado® Design Suite
Simulation
For supported simulators, see the
Xilinx Design Tools: Release Notes Guide
Synthesis
Synplify PRO
Vivado Synthesis
Support
Provided by Xilinx at the Xilinx Support web page
Notes:
1. For a complete list of supported devices, see the Vivado IP
catalog.
2. For the supported versions of the tools, see the Xilinx Design
Tools: Release Notes Guide.
