代码_DUC的cic_partlyb85_musicaljfo_数字上变频duc_数字上变频

共22个文件

m：8个

mat：5个

mdl：4个

版权申诉

数字上变频

5星 · 超过95%的资源 193 浏览量 2021-09-10 19:21:02 上传评论收藏 9.3MB RAR 举报

在IT领域，数字上变频（Digital Up-Conversion，DUC）是一种常见的信号处理技术，广泛应用于通信系统、音频处理和雷达系统等。本项目"代码_DUC的cic_partlyb85_musicaljfo_数字上变频duc_数字上变频"主要涉及了数字上变频的实现，通过模拟仿真展示了其工作原理。数字上变频的基本概念是将一个低频或基带信号转换到高频域，以便于在射频(RF)传输或者在不同频率范围进行处理。这个过程通常包括三个主要步骤：混频、频率偏移和增益控制。 1. **混频**：混频是数字上变频的核心，它通过将输入的基带信号与一个叫做本地振荡器(LO)的高频率信号相乘来实现。在数字领域，这一过程通常由数字乘法器或者快速傅里叶变换(FFT)实现。乘法的结果包含了原信号的频率成分以及LO的频率成分，经过适当的滤波处理，可以提取出目标的上变频信号。 2. **频率偏移**：在混频后，信号的中心频率会移动到新的位置，这个位置等于输入信号频率加上LO的频率。为了达到特定的上变频效果，需要选择合适的LO频率。 3. **增益控制**：上变频过程中可能会引入非线性失真，因此需要对信号进行增益控制以确保信号质量。这通常通过自动增益控制(AGC)算法来实现，以维持输出信号的恒定功率。在本项目中，"cic_partlyb85_musicaljfo"可能是某种特定的滤波器或者算法的名称，CIC（全称为Cascade Integrator-Comb）滤波器是一种常用于数字下变频(DDC)和上变频(DUC)的高效滤波结构，因其简单的硬件实现而受欢迎。"partlyb85"和"musicaljfo"可能代表项目中的特定配置或者参数，具体含义需要查看源代码才能明确。文件列表中的"duc"可能是指DUC的实现代码文件，包含有实现数字上变频功能的算法和程序。通过阅读和分析这些代码，我们可以深入理解DUC的工作流程，包括信号处理的细节、参数选择的影响以及如何优化性能。这个项目提供了一个实践性的学习平台，帮助我们理解和应用数字上变频技术，对于通信工程、信号处理或者软件定义无线电(SDR)领域的开发者来说，具有很高的参考价值。通过研究该项目，我们可以掌握数字上变频的基本原理，熟悉相关算法，并能动手实现和调试自己的DUC系统。

资源推荐

资源详情

资源评论

收起资源包目录

代码,代码编程教学,matlab源码.rar （22个子文件）

duc

model

plot_mcgsm_tx_mask.m 5KB

duc_dds_capture.mdl 81KB

gen_duc_sinusoid.m 421B

gmsk_mod.mdl 44KB

results

gmsk_mod_demo.mdl 29KB

scale_coeffs.m 1KB

duc_dds_capture_sysgen_error.log 2KB

analyze_duc_dds.m 4KB

gsm_duc_cic_filters.m 11KB

gsm_duc_cic_model.m 13KB

Designing Efficient Digital Up and Down.pdf 1.82MB

sysgen

gsm_duc_cic_init.m 80B

results

yp_duc.mat 23KB

scaled_yc_duc.mat 136KB

ycic_duc.mat 10.02MB

yc_duc.mat 136KB

gmsk_data_comp.mat 145KB

analyze_duc.m 27KB

SysgenFeatureReport.htm 13KB

duc_dds_capture_sysgen_warning.log 2KB

gsm_duc_cic.mdl 387KB

duc_dds_capture_sysgen.log 0B

XAPP1113 (v1.0) November 21, 2008 www.xilinx.com 1

of their respective owners.

Summary Digital Up Converters (DUC) and Digital Down Converters (DDC) are key components of RF

systems in communications, sensing, and imaging. This application note demonstrates how

efficient DUC/DDC implementations can be created by leveraging Xilinx® DSP tools and IP

portfolio for increased productivity and reduced development time. While previous application

notes

[Ref 1] have provided examples of DUC and DDC implementation in wideband

communications systems, this document concentrates on narrowband systems and the

building block components available to meet the particular requirements of such designs.

Step-by-step guidance is provided on how to perform simulation of narrowband DUC/DDC

systems in MATLAB®, how to map functions onto building blocks and IP cores for Xilinx®

FPGAs in System Generator software, and how to verify the implementation against the

simulation model. Two examples are provided: a multi-carrier GSM system (both DUC and

DDC) and a multi-channel MRI receiver (DDC only). The examples provide a guide and

template for implementation of customer-specific solutions and, in many cases, may be readily

adapted to customers’ own application systems. Advantages and limitations of the approaches

and methods employed are identified such that the reader can consider these in their own

system context.

Introduction In terms of signal processing, narrowband systems are generally characterized by the fact that

the bandwidth of the signal of interest is significantly less than the sampled bandwidth; that is,

a narrow band of frequencies must be selected and filtered out from a much wider spectral

window in which the signal might occur. This means that large sample rate changes (in the

hundreds or even thousands) must be undertaken to efficiently process the signal for either

transmission or reception. Examples of such systems include: communications systems, where

several narrow channels must be recovered from a wider transmission band, or medical

imaging systems, such as MRI, where the detected waveforms occur in a narrow range of

frequencies at varying points within a wider spectrum, as well as many other systems that fall

within this grouping.

[Ref 1] deals with wideband systems, providing guidance on how to select an appropriate

cascaded FIR structure to meet the sample rate change requirements of wireless base

stations. When the desired sample rate change is 32 or more, it is advisable to consider the use

of CIC filters. CIC filters are an alternative class of filters to FIR filters, and they are well-suited

to large sample rate changes, as they can be implemented efficiently in digital circuits. They are

often used in conjunction with small Finite Impulse Response (FIR) filters to implement the filter

chain of up- and down-converters in narrowband systems. While such converters have been

implemented often for many years in both Application Specific Standard Products (ASSPs) and

FPGAs, these have generally provided only single-channel solutions, or multiple instances

thereof. The latest high-density FPGA families with advanced architectures, in combination with

efficient IP cores and effective design tools, provide the capability to handle many channels

simultaneously. This application note demonstrates how to implement such designs.

Highlights:

• DUC and DDC design files for 4-carrier GSM, targeting Virtex®-5 FPGAs

Application Note: Virtex-5 Family

XAPP1113 (v1.0) November 21, 2008

Designing Efficient Digital Up and Down

Converters for Narrowband Systems

Author: Stephen Creaney and Igor Kostarnov

Introduction

XAPP1113 (v1.0) November 21, 2008 www.xilinx.com 2

• DDC design files for multi-channel MRI, targeting both Virtex-5 and Spartan®-DSP

FPGAs

• Designed using class-leading Xilinx® DSP IP portfolio

• Design flow for System Generator software for both designs

• Automatic scripted generation of implementation schematics based on system parameters

for the MRI design.

System Requirements

This application note was designed using MATLAB version 7.3.0 (R2006b) and the unified

release of the Xilinx® ISE® and DSP tools (System Generator) version 10.1.

Additional Reading

It is recommended that the reader be familiar with data sheets for the Xilinx® Cascaded

Integrator Comb (CIC) Compiler

[Ref 2], Direct Digital Synthesizer (DDS) Compiler [Ref 3], and

Finite Impulse Response (FIR) Compiler [Ref 4] IP cores.

A reasonable level of familiarity with Xilinx tools, in general, and System Generator software, in

particular, is assumed. Further information can be found in the software manuals

[Ref 5]

provided on the Xilinx website.

Acronyms and Abbreviations

Table 1: Acronyms and Abbreviations

3GPP 3rd Generation Partnership Project

ADC Analog-to-Digital Converter

AGC Automatic Gain Correction

ASIC Application Specific Integrated Circuit

ASSP Application Specific Standard Product

Block RAM Block Random Access Memory (Xilinx device resource)

BS Base Station

BT Bandwidth-Time

BTS Base Transceiver Station

CapEx Capital Expenditure

CFR Crest Factor Reduction

CIC Cascaded Integrator Comb

CFIR Compensation Finite Impulse Response Filter

DAC Digital-to-Analog Converter

dB Decibel

DDC Digital Down Converter

DDS Direct Digital Synthesizer

DFE Digital Front End

DPD Digital Pre-Distortion

DSP Digital Signal Processing/Processor

DUC Digital Up Converter

EDGE Enhanced Data rates for GSM Evolution

EDGE2 or e-EDGE Evolved EDGE

FPGA Field Programmable Gate Array

FID Free-Induction Decay

FIR Finite Impulse Response

Introduction

XAPP1113 (v1.0) November 21, 2008 www.xilinx.com 3

GMSK Gaussian Minimum Shift Keying

GSM Global System for Mobile Communication, originated from

Groupe Spécial Mobile

GUI Graphical User Interface

HDL Hardware Description Language

HOR Hardware Over-sampling Rate

IF Intermediate Frequency

IMD Inter-Modulation Distortion

ISI Inter-Symbol Interference

kbaud Kilo-baud (1,000 symbols per second)

ksps Kilo-samples per second (1,000 samples per second)

LSB Least Significant Bit(s)

LPF Low Pass Filter

LUT Look-Up Table

MAC Multiply-Accumulate

MRI Magnetic Resonance Imaging

MSB Most Significant Bit(s)

MSK Minimum Shift Keying

Msps Mega-samples per second (1,000,000 samples per second)

NCO Numerically Controlled Oscillator

OpEx Operation Expenditures

PA Power Amplifier

PAPR Peak-to-Average Power Ratio

PAR Place and Route

PFIR Pulse-Shaping Finite Impulse Response (Filter)

PSD Power Spectral Density

RMS Root Mean Square

RRC Root-Raised Cosine

RRH Remote Radio Head

SFDR Spurious-Free Dynamic Range

SNR Signal-to-Noise Ratio

TDDM Time Division De-Multiplex

TDM Time Division Multiplex

XST Xilinx Synthesis Technology

Table 1: Acronyms and Abbreviations (Cont’d)

Contents

XAPP1113 (v1.0) November 21, 2008 www.xilinx.com 4

Contents Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

System Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2

Additional Reading . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2

Acronyms and Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2

Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

Figures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

Tables. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

Digital Up Converters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

Digital Down Converters (DDC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

Building Blocks for Narrowband DUC/DDC Systems. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

Mixers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

Direct Digital Synthesizers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

Finite Impulse Response Filters. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

CIC Filters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

Critical Design Parameters for DUC/DDC Systems . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

Total Rate Change . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

Clock Rate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

Number of Carriers (or Subcarriers). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

Number of Channels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

Modulation Scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

Supported Standards . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

Application Example: Multi-Carrier GSM (MC-GSM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

Digital Up-Converter. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

Performance Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

DUC Input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

DUC Filter Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

Frequency Translation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

DUC Modeling and Performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

DUC Implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

Synthesis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

DUC Verification. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

DUC Resource Utilization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

DUC Power Consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

Limitations of CIC-based DUC Implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44

Digital Down-Converter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45

Performance Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45

DDC Input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46

Frequency Translation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46

DDC Filter Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47

DDC Modeling and Performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51

DDC Implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55

Synthesis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57

DDC Verification. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58

DDC Resource Utilization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61

Limitations of CIC-Based DDC Implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62

Application Example: Multi-Channel MRI Receiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62

Design Files . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62

Application Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63

Digital Down-Converter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64

Architectural Consideration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64

Performance Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65

Input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66

Modeling. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66

Filter Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67

Frequency Translation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70

Implementation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70

Synthesis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72

Verification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72

Resource Utilization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73

Individual Channel Implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73

Power Consumption. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75

Conclusion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76

References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76

Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78

Notice of Disclaimer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78

Figures

XAPP1113 (v1.0) November 21, 2008 www.xilinx.com 5

Figures Figure 1. Generic DUC architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

Figure 2. Generic DDC Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

Figure 3. Virtex-5 FPGA DSP48E Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

Figure 4. Two-Stage Mixing of Multi-Carrier Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

Figure 5. Block Diagram of the DDS Compiler Block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

Figure 6. SFDR Performance of Taylor Series Corrected DDS with Swept Frequency . . . . . . . . . . . . . . . . . . . 12

Figure 7. DDS Compiler Token and GUI in System Generator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

Figure 8. Single MAC FIR Filter Implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

Figure 9. FIR Compiler Token and GUI in System Generator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

Figure 10. CIC Component Stages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

Figure 11. CIC Decimation and Interpolation Structures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

Figure 12. Example CIC Magnitude Response Plot . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

Figure 13. CIC passband Aliasing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

Figure 14. CIC Passband Imaging . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

Figure 15. Illustration of Passband Droop Compensation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

Figure 16. CIC Compiler Token and GUI in System Generator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

Figure 17. GSM Transmission Spectral Mask . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

Figure 18. Spectrum of GMSK Modulated Signal. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

Figure 19. Scatter Plot of GMSK Modulated Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

Figure 20. Eye Diagram of GMSK Modulated Data, Illustrating Frequency Trajectories . . . . . . . . . . . . . . . . . . 27

Figure 21. Spectral Comparison of GSM and EDGE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

Figure 22. 3-Stage CIC-Based DUC Filtering. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

Figure 23. Magnitude Response of CIC Filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

Figure 24. Magnitude Response of CFIR Filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

Figure 25. Passband Zoom Overlay of CIC, CFIR, and Combined Frequency Responses . . . . . . . . . . . . . . . . 32

Figure 26. Overall DUC Filter Response . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

Figure 27. Overlay of DUC Filter Responses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

Figure 28. CFIR Output Power Spectral Density . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

Figure 29. CIC Filter Output Power Spectral Density . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

Figure 30. PSD of DDS Generated Carriers vs. Ideal Sinusoidal Carriers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

Figure 31. Single Carrier Mixed with -900 kHz Carrier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

Figure 32. Power Spectral Density for Multi-Carrier GSM Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

Figure 33. Top-Level Block Diagram for MC-GSM DUC Implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

Figure 34. Virtex-5 Mixer FPGA Implementation in System Generator Software. . . . . . . . . . . . . . . . . . . . . . . . 39

Figure 35. Complex Mixer Implementation with Cascaded DSP48 Slices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

Figure 36. Comparative Analysis of CFIR Output Results – Exact Match . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

Figure 37. Comparative Analysis of Up-Mixed Multi-Carrier Signal – Exact Match . . . . . . . . . . . . . . . . . . . . . . 42

Figure 38. Zoom of Up-Mixed Multi-Carrier Signal Comparison. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42

Figure 39. Relaxed GSM Reception Spectral Mask . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46

Figure 40. 3-Stage CIC-Based DDC Filtering. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47

Figure 41. Magnitude Response of CIC Filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48

Figure 42. Magnitude Response of CFIR Filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49

Figure 43. Passband Zoom Overlay of CIC, CFIR, and Combined Frequency Responses . . . . . . . . . . . . . . . . 49

Figure 44. Magnitude Response of PFIR Filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50

Figure 45. Overall DUC Filter Response . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50

Figure 46. Overlay of DDC Filter Responses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51

Figure 47. DDC Input Signal. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

. . . . . . . . . . . . . . 52

Figure 48. PSD of DDS Generated Carriers vs. Ideal Sinusoidal Carriers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52

Figure 49. Received Signal Spectra Shifted by -900 kHz and +300 kHz Carriers . . . . . . . . . . . . . . . . . . . . . . . 53

Figure 50. CIC Filter Output Power Spectral Density . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53

Figure 51. CFIR Output Power Spectral Density . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54

Figure 52. PFIR Output Power Spectral Density . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54

Figure 53. Top-Level Block Diagram for MC-GSM DDC Implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55

Figure 54. Virtex-5 FPGA Mixer Implementation in System Generator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56

Figure 55. Comparative Analysis of Down-Mixed Signal, Channel 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58

Figure 56. Zoom of Down-Mixed Signal Comparison, Channel 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58

Figure 57. Comparative Analysis of CIC Output Results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59

Figure 58. Comparative Analysis of CFIR Output Results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59

Figure 59. Comparative Analysis of PFIR Output Results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60

Figure 60. MRI Scanner Equipment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63

Figure 61. MRI Pre-amplifier and Converter Context . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64

Figure 62. MRI DDC CIC Frequency Response. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67

Figure 63. CFIR Frequency Response . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68

Figure 64. Combined Frequency Response of Filter Cascade. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68

Figure 65. Passband Zoom of Compensated Frequency Response . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69

Figure 66. Single Channel DDC for MRI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71

Figure 67. 8-Channel DDC for MRI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73