################################################################################
# Vivado (TM) v2020.2 (64-bit)
#
# README.txt: Please read the sections below to understand the steps required
# to simulate the design for a simulator, the directory structure
# and the generated exported files.
#
################################################################################
1. Simulate Design
To simulate design, cd to the simulator directory and execute the script.
For example:-
% cd questa
% ./top.sh
The export simulation flow requires the Xilinx pre-compiled simulation library
components for the target simulator. These components are referred using the
'-lib_map_path' switch. If this switch is specified, then the export simulation
will automatically set this library path in the generated script and update,
copy the simulator setup file(s) in the exported directory.
If '-lib_map_path' is not specified, then the pre-compiled simulation library
information will not be included in the exported scripts and that may cause
simulation errors when running this script. Alternatively, you can provide the
library information using this switch while executing the generated script.
For example:-
% ./top.sh -lib_map_path /design/questa/clibs
Please refer to the generated script header 'Prerequisite' section for more details.
2. Directory Structure
By default, if the -directory switch is not specified, export_simulation will
create the following directory structure:-
<current_working_directory>/export_sim/<simulator>
For example, if the current working directory is /tmp/test, export_simulation
will create the following directory path:-
/tmp/test/export_sim/questa
If -directory switch is specified, export_simulation will create a simulator
sub-directory under the specified directory path.
For example, 'export_simulation -directory /tmp/test/my_test_area/func_sim'
command will create the following directory:-
/tmp/test/my_test_area/func_sim/questa
By default, if -simulator is not specified, export_simulation will create a
simulator sub-directory for each simulator and export the files for each simulator
in this sub-directory respectively.
IMPORTANT: Please note that the simulation library path must be specified manually
in the generated script for the respective simulator. Please refer to the generated
script header 'Prerequisite' section for more details.
3. Exported script and files
Export simulation will create the driver shell script, setup files and copy the
design sources in the output directory path.
By default, when the -script_name switch is not specified, export_simulation will
create the following script name:-
<simulation_top>.sh (Unix)
When exporting the files for an IP using the -of_objects switch, export_simulation
will create the following script name:-
<ip-name>.sh (Unix)
Export simulation will create the setup files for the target simulator specified
with the -simulator switch.
For example, if the target simulator is "ies", export_simulation will create the
'cds.lib', 'hdl.var' and design library diectories and mappings in the 'cds.lib'
file.
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数字信号处理----数字上变频&下变频--FPGA实现
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数字上变频器(DUC)和数字下变频器(DDC)广泛应用于通信系统,用于信号采样速率的转换。当信号从基带转换至中频( IF )带,需要使用数字上变频器。而数字下变频器是用于将信号从中频( IF )带转换为基带。DUC和DDC通常包括使用混频器进行频率转换,此外还有采样率转换。DUC或DDC的结构主要取决于所需要的转换率。例如,WiMAX (全球互通微波接入)系统典型的转换率为8—10阶。对于如此低的转换率,DUC和DDC只需采用FIR滤波器架构。如果需要更高的转换率,DDC / DUC结构中需要使用级联积分梳状(CIC)滤波器。DDC用于滤波和降低输出数据速率。该数字处理部分包括数控振荡器:NCO(Nu-merical Control Oscillator)、半带抽取滤波器、FIR滤波器、增益级和复数-实数转换级。各处理模块都有控制线路,能单独使能。 配合文章https://blog.csdn.net/Born_toward/article/details/123221134?spm=1001.2014.3001.5502使用,以余弦信号的上下变频为例,通过DDC &DUC恢复原始信号。
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数字信号处理----数字上变频&下变频--FPGA实现 (519个子文件)
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xsim.ini.bak 30KB
elaborate.bat 2KB
compile.bat 1KB
simulate.bat 1021B
runme.bat 229B
runme.bat 229B
runme.bat 229B
runme.bat 229B
runme.bat 229B
runme.bat 229B
runme.bat 229B
duc1.bd 22KB
duc1.bda 2KB
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duc1.bda 2KB
duc1.bda 2KB
duc1.bxml 3KB
xsim_3.c 279KB
xsim_1.c 54KB
FIR_BPF_99_1_5M.coe 545B
FIR_BPF_99_1_5M.coe 545B
FIR_BPF_99_1_5M.coe 545B
FIR_BPF_99_1_5M.coe 545B
FIR_BPF_99_1_5M.coe 545B
FIR_BPF_99_1_5M.coe 545B
FIR_BPF_99_1_5M.coe 545B
FIR_BPF_99_1_5M.coe 545B
FIR_BPF_99_1_5M.coe 545B
FIR_BPF_99_1_5M.coe 545B
xsim.dbg 29KB
duc1_dds_compiler_0_0.dcp 101KB
duc1_dds_compiler_0_0.dcp 101KB
duc1_dds_compiler_0_1.dcp 101KB
duc1_dds_compiler_0_1.dcp 101KB
duc1_mult_gen_0_0.dcp 101KB
duc1_mult_gen_0_0.dcp 101KB
duc1_mult_gen_0_1.dcp 101KB
duc1_mult_gen_0_1.dcp 101KB
duc1_mult_gen_0_0.dcp 101KB
duc1_dds_compiler_0_0.dcp 101KB
duc1_dds_compiler_1_0.dcp 101KB
duc1_dds_compiler_1_0.dcp 101KB
duc1_dds_compiler_0_1.dcp 101KB
duc1_dds_compiler_0_2.dcp 101KB
duc1_dds_compiler_0_2.dcp 101KB
duc1_dds_compiler_0_2.dcp 100KB
duc1_dds_compiler_1_0.dcp 100KB
duc1_c_addsub_0_0.dcp 54KB
duc1_c_addsub_0_0.dcp 54KB
duc1_c_addsub_0_0.dcp 54KB
compile.do 5KB
compile.do 5KB
compile.do 5KB
compile.do 5KB
simulate.do 608B
simulate.do 598B
simulate.do 598B
elaborate.do 487B
simulate.do 178B
wave.do 32B
wave.do 32B
wave.do 32B
wave.do 32B
simulate.do 11B
xsimk.exe 2.06MB
run.f 4KB
run.f 4KB
duc1.hwdef 17KB
duc1.hwh 142KB
.xsim_webtallk.info 65B
xsim.ini 30KB
xsim.ini 29KB
xsimSettings.ini 1KB
webtalk_1988.backup.jou 845B
webtalk.jou 845B
webtalk_7000.backup.jou 845B
vivado.jou 809B
vivado.jou 809B
vivado.jou 808B
vivado.jou 808B
vivado.jou 781B
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vivado.jou 780B
ISEWrap.js 8KB
ISEWrap.js 8KB
ISEWrap.js 8KB
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