+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Legal Partition Candidates ;
+-------------------------------------------+-------+----------------+--------------+----------------+--------+-----------------+---------------+-----------------+-------+----------------+--------------+------------------+-------------------+
; Hierarchy ; Input ; Constant Input ; Unused Input ; Floating Input ; Output ; Constant Output ; Unused Output ; Floating Output ; Bidir ; Constant Bidir ; Unused Bidir ; Input only Bidir ; Output only Bidir ;
+-------------------------------------------+-------+----------------+--------------+----------------+--------+-----------------+---------------+-----------------+-------+----------------+--------------+------------------+-------------------+
; TLT_pll_u|altpll_component|auto_generated ; 2 ; 0 ; 0 ; 0 ; 5 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ;
; TLT_pll_u ; 1 ; 0 ; 0 ; 0 ; 2 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ;
+-------------------------------------------+-------+----------------+--------------+----------------+--------+-----------------+---------------+-----------------+-------+----------------+--------------+------------------+-------------------+
PLL_锁相环程序_PLL_锁相程序_ （159个子文件） 
_info 2KB _vmake 26B PLL.vpr.ammdb 422B PLL.root_partition.cmp.ammdb 237B PLL.map.ammdb 129B PLL.vt.bak 3KB PLL_run_msim_rtl_verilog.do.bak 864B PLL.v.bak 0B PLL_run_msim_rtl_verilog.do.bak1 864B PLL_run_msim_rtl_verilog.do.bak2 864B PLL_run_msim_rtl_verilog.do.bak3 864B PLL_run_msim_rtl_verilog.do.bak4 864B PLL_run_msim_rtl_verilog.do.bak5 864B PLL_run_msim_rtl_verilog.do.bak6 808B PLL_run_msim_rtl_verilog.do.bak7 808B PLL.cmp.bpm 784B PLL.map.bpm 681B PLL.cmp.cdb 4KB PLL.rtlv_sg.cdb 4KB PLL.rtlv_sg_swap.cdb 3KB PLL.root_partition.cmp.cdb 3KB PLL.map.cdb 3KB PLL.root_partition.map.cdb 3KB PLL.root_partition.map.hbdb.cdb 3KB PLL.sgdiff.cdb 2KB PLL.(1).cnf.cdb 2KB PLL.map_bb.cdb 2KB PLL.(2).cnf.cdb 2KB PLL.(3).cnf.cdb 1KB PLL.(0).cnf.cdb 944B PLL.root_partition.map.reg_db.cdb 217B _primary.dat 4KB _primary.dat 2KB logic_util_heursitic.dat 880B _primary.dat 439B _primary.dat 249B PLL.db_info 140B PLL.db_info 140B _primary.dbs 2KB _primary.dbs 1KB _primary.dbs 728B _primary.dbs 349B PLL.tiscmp.fast_1200mv_n40c.ddb 106KB PLL.tiscmp.slow_1200mv_n40c.ddb 106KB PLL.tiscmp.slow_1200mv_125c.ddb 105KB PLL.tiscmp.fastest_slow_1200mv_85c.ddb 101KB PLL.tiscmp.fastest_slow_1200mv_n40c.ddb 101KB PLL.asm_labs.ddb 6KB PLL.tis_db_list.ddb 316B PLL.pti_db_list.ddb 246B PLL.root_partition.cmp.dfp 33B PLL_run_msim_rtl_verilog.do 808B PLL.done 26B PLL.root_partition.map.dpi 4KB PLL.root_partition.map.hbdb.hb_info 48B PLL.pre_map.hdb 18KB PLL.rtlv.hdb 16KB PLL.sgdiff.hdb 15KB PLL.cmp.hdb 12KB PLL.root_partition.cmp.hdb 12KB PLL.map.hdb 11KB PLL.root_partition.map.hdb 11KB PLL.root_partition.map.hbdb.hdb 11KB PLL.map_bb.hdb 10KB PLL.(1).cnf.hdb 1KB PLL.(2).cnf.hdb 1KB PLL.(3).cnf.hdb 976B PLL.(0).cnf.hdb 686B PLL.hier_info 2KB PLL.hif 3KB PLL.cycloneive_io_sim_cache.45um_ff_1200mv_n40c_fast.hsd 733KB PLL.cycloneive_io_sim_cache.45um_ii_1200mv_85c_slow.hsd 732KB PLL.cycloneive_io_sim_cache.45um_ii_1200mv_125c_slow.hsd 732KB PLL.cycloneive_io_sim_cache.45um_ii_1200mv_n40c_slow.hsd 730KB
PLL.lpc.html 812B PLL.cmp.idb 1KB modelsim.ini 11KB PLL.ipinfo 380B PLL.jdi 221B PLL.cmp_merge.kpt 207B PLL.root_partition.map.kpt 207B PLL.root_partition.cmp.kpt 205B PLL.map.kpt 205B .cmp.kpt 202B PLL.cmp.logdb 8KB PLL.root_partition.cmp.logdb 4B PLL.map.logdb 4B PLL.map_bb.logdb 4B msim_transcript 3KB PLL.pin 20KB TLT_pll.ppf 428B verilog.prw 2KB verilog.prw 1KB verilog.prw 278B verilog.prw 71B verilog.psm 31KB verilog.psm 13KB verilog.psm 4KB verilog.psm 2KB PLL_assignment_defaults.qdf 46KB共 159 条
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