SOC testing.1
SOC Testing
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SOC Test Problems/requirements
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IEEE P1500 Standard
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SOC Test Methodology
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Testable SOC Design Flow
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Conclusions
SOC testing.2
SOC Test Problems
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Deeply embedded cores
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More, higher-performance core pins than SOC pins
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External ATE inefficiency
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Mixing technologies: logic, processor, memory,
analog components
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Multiple hardware description levels for cores
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Different core providers and SOC test developers
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Core/test reuse
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Hierarchical core reuse
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IP protection
SOC testing.3
SOC Test Requirements
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Deeply embedded cores
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Need Test Access Mechanism
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More, higher-performance core pins than SOC pins
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Need on-chip, at-speed testing
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External ATE inefficiency
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Need “on-chip ATE”
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Mixing technologies: logic, processor, memory,
analog components
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Need various DFT/BIST/ techniques
SOC testing.4
SOC Test Requirements (cont.)
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Multiple hardware description level for cores
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Need to insert DFT/BIST at various levels
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Different core providers and SOC test developers
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Need standard for test integration
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Core/test reuse
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Need plug-and-play test mechanism
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Hierarchical core reuse
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Need hierarchical test management
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IP protection
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Need core test standard/document
SOC testing.5
Core Test Techniques
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Single scan
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Multiple scan
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Broadcast scan
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Enabled ATPG – Scan insertion
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Reusable ATPG – Access & isolation
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Test point insertion
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Shadow register
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Enabled BIST – Scan, test points
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Embedded BIST – Serial or parallel, local
controller, TPG and SA
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Boundary scan (BS)