/* Based on CPU DB MC9S12XS256_112, version 3.00.000 (RegistersPrg V2.23) */
/* DataSheet : MC9S12XS256RMV1 Rev. 1.01 08/2007 */
#include <mc9s12xs128.h>
/*lint -save -esym(765, *) */
/* * * * * 8-BIT REGISTERS * * * * * * * * * * * * * * * */
volatile PORTESTR _PORTE; /* Port E Data Register; 0x00000008 */
volatile DDRESTR _DDRE; /* Port E Data Direction Register; 0x00000009 */
volatile MODESTR _MODE; /* Mode Register; 0x0000000B */
volatile PUCRSTR _PUCR; /* Pull-Up Control Register; 0x0000000C */
volatile RDRIVSTR _RDRIV; /* Reduced Drive Register; 0x0000000D */
volatile GPAGESTR _GPAGE; /* Global Page Index Register; 0x00000010 */
volatile DIRECTSTR _DIRECT; /* Direct Page Register; 0x00000011 */
volatile MMCCTL1STR _MMCCTL1; /* MMC Control Register; 0x00000013 */
volatile PPAGESTR _PPAGE; /* Program Page Index Register; 0x00000015 */
volatile RPAGESTR _RPAGE; /* RAM Page Index Register; 0x00000016 */
volatile EPAGESTR _EPAGE; /* Data FLASH Page Index Register; 0x00000017 */
volatile ECLKCTLSTR _ECLKCTL; /* ECLK Control Register; 0x0000001C */
volatile IRQCRSTR _IRQCR; /* Interrupt Control Register; 0x0000001E */
volatile DBGC1STR _DBGC1; /* Debug Control Register 1; 0x00000020 */
volatile DBGSRSTR _DBGSR; /* Debug Status Register; 0x00000021 */
volatile DBGTCRSTR _DBGTCR; /* Debug Trace Control Register; 0x00000022 */
volatile DBGC2STR _DBGC2; /* Debug Control Register 2; 0x00000023 */
volatile DBGCNTSTR _DBGCNT; /* Debug Count Register; 0x00000026 */
volatile DBGSCRXSTR _DBGSCRX; /* Debug State Control Register; 0x00000027 */
volatile DBGXCTLSTR _DBGXCTL; /* Debug Comparator Control Register; 0x00000028 */
volatile DBGXAHSTR _DBGXAH; /* Debug Comparator Address High Register; 0x00000029 */
volatile DBGXAMSTR _DBGXAM; /* Debug Comparator Address Mid Register; 0x0000002A */
volatile DBGXALSTR _DBGXAL; /* Debug Comparator Address Low Register; 0x0000002B */
volatile DBGXDHSTR _DBGXDH; /* Debug Comparator Data High Register; 0x0000002C */
volatile DBGXDLSTR _DBGXDL; /* Debug Comparator Data Low Register; 0x0000002D */
volatile DBGXDHMSTR _DBGXDHM; /* Debug Comparator Data High Mask Register; 0x0000002E */
volatile DBGXDLMSTR _DBGXDLM; /* Debug Comparator Data Low Mask Register; 0x0000002F */
volatile PORTKSTR _PORTK; /* Port K Data Register; 0x00000032 */
volatile DDRKSTR _DDRK; /* Port K Data Direction Register; 0x00000033 */
volatile SYNRSTR _SYNR; /* S12XECRG Synthesizer Register; 0x00000034 */
volatile REFDVSTR _REFDV; /* S12XECRG Reference Divider Register; 0x00000035 */
volatile POSTDIVSTR _POSTDIV; /* S12XECRG Post Divider Register; 0x00000036 */
volatile CRGFLGSTR _CRGFLG; /* S12XECRG Flags Register; 0x00000037 */
volatile CRGINTSTR _CRGINT; /* S12XECRG Interrupt Enable Register; 0x00000038 */
volatile CLKSELSTR _CLKSEL; /* S12XECRG Clock Select Register; 0x00000039 */
volatile PLLCTLSTR _PLLCTL; /* S12XECRG IPLL Control Register; 0x0000003A */
volatile RTICTLSTR _RTICTL; /* S12XECRG RTI Control Register; 0x0000003B */
volatile COPCTLSTR _COPCTL; /* CRG COP Control Register; 0x0000003C */
volatile ARMCOPSTR _ARMCOP; /* CRG COP Timer Arm/Reset Register; 0x0000003F */
volatile TIOSSTR _TIOS; /* Timer Input Capture/Output Compare Select; 0x00000040 */
volatile CFORCSTR _CFORC; /* Timer Compare Force Register; 0x00000041 */
volatile OC7MSTR _OC7M; /* Output Compare 7 Mask Register; 0x00000042 */
volatile OC7DSTR _OC7D; /* Output Compare 7 Data Register; 0x00000043 */
volatile TSCR1STR _TSCR1; /* Timer System Control Register1; 0x00000046 */
volatile TTOVSTR _TTOV; /* Timer Toggle On Overflow Register; 0x00000047 */
volatile TCTL1STR _TCTL1; /* Timer Control Register 1; 0x00000048 */
volatile TCTL2STR _TCTL2; /* Timer Control Register 2; 0x00000049 */
volatile TCTL3STR _TCTL3; /* Timer Control Register 3; 0x0000004A */
volatile TCTL4STR _TCTL4; /* Timer Control Register 4; 0x0000004B */
volatile TIESTR _TIE; /* Timer Interrupt Enable Register; 0x0000004C */
volatile TSCR2STR _TSCR2; /* Timer System Control Register 2; 0x0000004D */
volatile TFLG1STR _TFLG1; /* Main Timer Interrupt Flag 1; 0x0000004E */
volatile TFLG2STR _TFLG2; /* Main Timer Interrupt Flag 2; 0x0000004F */
volatile PACTLSTR _PACTL; /* 16-Bit Pulse Accumulator A Control Register; 0x00000060 */
volatile PAFLGSTR _PAFLG; /* Pulse Accumulator A Flag Register; 0x00000061 */
volatile OCPDSTR _OCPD; /* Output Compare Pin Disconnect Register; 0x0000006C */
volatile PTPSRSTR _PTPSR; /* Precision Timer Prescaler Select Register; 0x0000006E */
volatile SCI0ACR2STR _SCI0ACR2; /* SCI 0 Alternative Control Register 2; 0x000000CA */
volatile SCI0CR2STR _SCI0CR2; /* SCI 0 Control Register 2; 0x000000CB */
volatile SCI0SR1STR _SCI0SR1; /* SCI 0 Status Register 1; 0x000000CC */
volatile SCI0SR2STR _SCI0SR2; /* SCI 0 Status Register 2; 0x000000CD */
volatile SCI0DRHSTR _SCI0DRH; /* SCI 0 Data Register High; 0x000000CE */
volatile SCI0DRLSTR _SCI0DRL; /* SCI 0 Data Register Low; 0x000000CF */
volatile SCI1ACR2STR _SCI1ACR2; /* SCI 1 Alternative Control Register 2; 0x000000D2 */
volatile SCI1CR2STR _SCI1CR2; /* SCI 1 Control Register 2; 0x000000D3 */
volatile SCI1SR1STR _SCI1SR1; /* SCI 1 Status Register 1; 0x000000D4 */
volatile SCI1SR2STR _SCI1SR2; /* SCI 1 Status Register 2; 0x000000D5 */
volatile SCI1DRHSTR _SCI1DRH; /* SCI 1 Data Register High; 0x000000D6 */
volatile SCI1DRLSTR _SCI1DRL; /* SCI 1 Data Register Low; 0x000000D7 */
volatile SPI0CR1STR _SPI0CR1; /* SPI 0 Control Register 1; 0x000000D8 */
volatile SPI0CR2STR _SPI0CR2; /* SPI 0 Control Register 2; 0x000000D9 */
volatile SPI0BRSTR _SPI0BR; /* SPI 0 Baud Rate Register; 0x000000DA */
volatile SPI0SRSTR _SPI0SR;
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