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<title>Sample Waveforms for memory.vhd </title>
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<h2><CENTER>Sample behavioral waveforms for design file memory.vhd </CENTER></h2>
<P>The following waveforms show the behavior of altsyncram megafunction for the chosen set of parameters in design memory.vhd. For the purpose of this simulation, the contents of the memory at the start of the sample waveforms is assumed to be ( FFF0, FFF1, FFF2, FFF3, ...). The design memory.vhd has one read port and one write port. The read port has 256 words of 16 bits each and the write port has 256 words of 16 bits each. The write core uses a different clock enable than the read input registers. The read core uses a different clock enable than the read input registers. The output of the read port is registered by rdclock. </P>
<CENTER><img src=memory_wave0.jpg> </CENTER>
<P><CENTER><FONT size=2>Fig. 1 : Wave showing read operation. </CENTER></P>
<P><FONT size=3>The above waveform shows the behavior of the design under normal read conditions. The read happens at the rising edge of the enabled clock cycle. The output from the RAM is undefined until after the first rising edge of the read clock. The clock enable on the read side input registers are disabled. The clock enable on the output registers are disabled. </P>
<CENTER><img src=memory_wave1.jpg> </CENTER>
<P><CENTER><FONT size=2>Fig. 2 : Waveform showing write operation </CENTER></P>
<P><FONT size=3>The above waveform shows the behavior of the design under normal write conditions. The write cycle is assumed to be from the rising edge of the enabled clock in which wren is high till the rising edge of the next clock cycle. In DUAL_PORT mode, when the write happens at the same address as the one being read in the other port, the read output is unknown. Actual write into the RAM happens at the rising edge or falling edge of the write clock, depending on whether the RAM blocks are assigned to M-RAM or not. In the sample waveforms, they are shown to be on the falling edge of the write clock. The clock enable on the write side input registers are disabled. The clock enable on the output registers are disabled. </P>
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ram.rar_ ram vh_RAM vh_RAMVH_vhdl ram 源代码 （210个子文件） 
ram.autos_3e92b2e5d298f5cf757a393f7655ccd81.map.atm 99KB ram.sldhu_30e344a040fd07e1533c49de5f2d67d1.map.atm 21KB ram.bdf 12KB ram.map.bpm 8KB ram.cmp.bpm 7KB memory.bsf 5KB add.bsf 2KB ram.cmp.cdb 147KB ram.sgdiff.cdb 39KB ram.map.cdb 38KB ram.(13).cnf.cdb 11KB ram.(17).cnf.cdb 10KB ram.(45).cnf.cdb 9KB ram.rtlv_sg.cdb 7KB ram.cmp_bb.cdb 7KB ram.(14).cnf.cdb 6KB ram.(18).cnf.cdb 5KB ram.(42).cnf.cdb 5KB ram.(53).cnf.cdb 5KB ram.(16).cnf.cdb 4KB ram.pre_map.cdb 4KB ram.(44).cnf.cdb 4KB ram.map_bb.cdb 3KB ram.(39).cnf.cdb 3KB ram.(37).cnf.cdb 3KB ram.(43).cnf.cdb 3KB ram.(25).cnf.cdb 3KB ram.(15).cnf.cdb 3KB ram.(46).cnf.cdb 3KB ram.(33).cnf.cdb 3KB ram.(28).cnf.cdb 3KB ram.(41).cnf.cdb 2KB ram.(36).cnf.cdb 2KB ram.rtlv_sg_swap.cdb 2KB ram.(35).cnf.cdb 2KB ram.(47).cnf.cdb 2KB ram.(8).cnf.cdb 2KB ram.(12).cnf.cdb 2KB ram.(7).cnf.cdb 2KB ram.(49).cnf.cdb 2KB ram.(26).cnf.cdb 2KB ram.(31).cnf.cdb 2KB ram.(2).cnf.cdb 2KB ram.(3).cnf.cdb 2KB ram.(5).cnf.cdb 2KB ram.(4).cnf.cdb 2KB ram.(10).cnf.cdb 2KB ram.(1).cnf.cdb 1KB ram.(23).cnf.cdb 1KB ram.(11).cnf.cdb 1KB ram.(6).cnf.cdb 1KB ram.(20).cnf.cdb 1KB ram.(21).cnf.cdb 1KB ram.(19).cnf.cdb 1KB ram.(22).cnf.cdb 1KB ram.(9).cnf.cdb 1KB ram.(0).cnf.cdb 1KB ram.(27).cnf.cdb 1KB ram.(51).cnf.cdb 1KB ram.(32).cnf.cdb 1KB ram.(40).cnf.cdb 1KB ram.(24).cnf.cdb 1KB ram.(34).cnf.cdb 1KB ram.(38).cnf.cdb 1KB ram.(52).cnf.cdb 1KB ram.(29).cnf.cdb 980B ram.(48).cnf.cdb 897B ram.(30).cnf.cdb 814B ram.(50).cnf.cdb 649B ram.signalprobe.cdb 382B ram.eco.cdb 160B ram.cdf 280B memory.cmp 1KB ram.db_info 136B ram.dbp 0B ram.cmp0.ddb 342KB ram.asm_labs.ddb 284KB ram.done 26B ram.dpf 239B ram.map.ecobp 68B ram.cmp.ecobp 68B ram.eds_overflow 3B ram.sgdiff.hdb 77KB ram.cmp.hdb 45KB ram.cmp_bb.hdb 45KB ram.map.hdb 44KB ram.map_bb.hdb 43KB ram.pre_map.hdb 14KB ram.rtlv.hdb 14KB ram.(13).cnf.hdb 5KB ram.(45).cnf.hdb 3KB ram.sim.hdb 3KB ram.(18).cnf.hdb 2KB ram.(14).cnf.hdb 2KB ram.(37).cnf.hdb 1KB ram.(16).cnf.hdb 1KB ram.(39).cnf.hdb 1KB ram.(53).cnf.hdb 1KB ram.(49).cnf.hdb 1013B ram.(17).cnf.hdb 975B共 210 条
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