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<title>Sample Waveforms for DOUBLRAM.vhd </title>
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<h2><CENTER>Sample behavioral waveforms for design file DOUBLRAM.vhd </CENTER></h2>
<P>The following waveforms show the behavior of altsyncram megafunction for the chosen set of parameters in design DOUBLRAM.vhd. For the purpose of this simulation, the contents of the memory at the start of the sample waveforms is assumed to be ( F0, F1, F2, F3, ...). The design DOUBLRAM.vhd has one read port and one write port. The read port has 256 words of 8 bits each and the write port has 256 words of 8 bits each. The output of the read port is registered by clock. </P>
<CENTER><img src=DOUBLRAM_wave0.jpg> </CENTER>
<P><CENTER><FONT size=2>Fig. 1 : Wave showing read operation. </CENTER></P>
<P><FONT size=3>The above waveform shows the behavior of the design under normal read conditions. The read happens at the rising edge of the enabled clock cycle. The output from the RAM is undefined until after the first rising edge of the read clock. Read enable port should be enabled for read in the simple dual port mode The clock enable on the read side input registers are disabled. The clock enable on the output registers are disabled. </P>
<CENTER><img src=DOUBLRAM_wave1.jpg> </CENTER>
<P><CENTER><FONT size=2>Fig. 2 : Waveform showing write operation </CENTER></P>
<P><FONT size=3>The above waveform shows the behavior of the design under normal write conditions. The write cycle is assumed to be from the rising edge of the enabled clock in which wren is high till the rising edge of the next clock cycle. In DUAL_PORT mode, when the write happens at the same address as the one being read in the other port, the read output is unknown. Actual write into the RAM happens at the falling edge of the write clock. The clock enable on the write side input registers are disabled. The clock enable on the output registers are disabled. </P>
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RAM.rar_RAM in VHDL_vhdl
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2022-09-24
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RAM.rar （86个子文件） 
RAM 
DOUBLRAM_waveforms.html 2KB WAVEDATA 
testRAMWR.vwf 11KB testRAMWR.sim.rpt 24KB RAMWR.inc 894B testRAMWR.jdi 21B testRAMWR.qpf 909B IIPORTRAM.bsf 5KB ADDRESS.vhd 464B RAMWR.cmp 1KB testRAMWR.qsf 3KB testRAMWR.asm.rpt 7KB FIFO.inc 918B DOUBLRAM.cmp 1KB testRAMWR.qws 2KB Delay.vhd.bak 263B IIPORTRAM_inst.vhd 191B
IIPORTRAM_wave1.jpg 141KB fifo3.vhd.bak 637B testRAMWR.bdf 8KB DOUBLRAM_inst.vhd 211B RAMWR_waveforms.html 2KB testRAMWR.tan.summary 2KB IIPORTRAM_wave0.jpg 103KB ADD8B.vhd 491B db testRAMWR.db_info 152B prev_cmp_testRAMWR.sim.qmsg 476KB altsyncram_nmf1.tdf 3KB altsyncram_el72.tdf 14KB decode_aoi.tdf 3KB altsyncram_6h92.tdf 14KB testRAMWR.eco.cdb 176B altsyncram_06q1.tdf 13KB wed.wsf 13KB altsyncram_47r1.tdf 13KB prev_cmp_testRAMWR.asm.qmsg 2KB prev_cmp_testRAMWR.tan.qmsg 41KB altsyncram_96c1.tdf 3KB prev_cmp_testRAMWR.map.qmsg 14KB testRAMWR.sld_design_entry.sci 169B altsyncram_s5b2.tdf 14KB prev_cmp_testRAMWR.fit.qmsg 42KB testRAMWR.sim.cvwf 2KB prev_cmp_testRAMWR.qmsg 476KB altsyncram_12e1.tdf 3KB testRAMWR.tan.rpt 60KB testRAMWR.fit.rpt 96KB ADDRESS.vhd.bak 497B RAMWR.bsf 4KB testRAMWR.pin 20KB DOUBLRAM_wave0.jpg 112KB FIFO.bsf 3KB RAMWR_wave1.jpg 128KB RAMWR_inst.vhd 147B testRAMWR.map.rpt 30KB testRAMWR.map.summary 460B testRAMWR.pof 512KB IIPORTRAM.cmp 1KB IIPORTRAM.inc 919B testRAMWR.fit.summary 596B IIPORTRAM.vhd 9KB DOUBLRAM_wave1.jpg 149KB IIPORTRAM_waveforms.html 2KB DOUBLRAM.inc 926B FIFO.cmp 1KB Delay.vhd 262B RAMWR.vhd 7KB DOUBLRAM.qip 547B testRAMWR.flow.rpt 9KB fifo3.vhd 639B FIFO_wave1.jpg 95KB ADD8B.vhd.bak 483B IIPORTRAM.qip 552B ADDRESS.bsf 2KB testRAMWR.sof 148KB RAMWR_wave0.jpg 103KB RAMWR.qip 532B FIFO.qip 520B DOUBLRAM.vhd 10KB FIFO_wave0.jpg 93KB FIFO.vhd 7KB testRAMWR.fit.smsg 513B testRAMWR.done 26B ADD8B.bsf 2KB FIFO_waveforms.html 1KB DOUBLRAM.bsf 5KB FIFO_inst.vhd 213B
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