1） 程序设计
串并行转换器设计
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY SHFRT IS -- 8 位右移寄存器
PORT ( CLK,LOAD,EN : IN STD_LOGIC;
QB : IN STD_LOGIC;
DOUT : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
);
END SHFRT;
ARCHITECTURE behav OF SHFRT IS
SIGNAL REG8 : STD_LOGIC_VECTOR(7 DOWNTO 0);
SIGNAL DBUF : STD_LOGIC_VECTOR(7 DOWNTO 0);
BEGIN
DOUT<=DBUF;
PR1: PROCESS (CLK,EN)
BEGIN
IF CLK'EVENT AND CLK = '1'
THEN IF EN='1'
THEN REG8(7 DOWNTO 1) <= REG8(6 DOWNTO 0);
REG8(0)<=QB; -- 输出最低位
ELSE REG8(7 DOWNTO 0) <= REG8(7 DOWNTO 0);
END IF;
END IF;
END PROCESS PR1;
RP2: PROCESS (CLK,LOAD)
BEGIN
IF CLK'EVENT AND CLK = '1'
THEN IF LOAD='1'
THEN DBUF<=REG8; --由（LOAD='1'）装载新数据
ELSE DBUF<=DBUF;
END IF;
END IF;
END PROCESS RP2;
END behav;
3.2 ADC 控制器设计
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY CONTR IS
PORT(
QB : IN STD_LOGIC;--INPUT SIGNAL
CLK : IN STD_LOGIC;--状态机工作时钟
EOC : OUT STD_LOGIC;--转换状态指示，低电平表示正在转换
