Copyright © 2001 ARM Limited. All rights reserved.
ARM DDI 0234B
ARM7TDMI-S
Revision: r4p3
Technical Reference Manual
ii Copyright © 2001 ARM Limited. All rights reserved. ARM DDI 0234B
ARM7TDMI-S
Technical Reference Manual
Copyright © 2001 ARM Limited. All rights reserved.
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Change history
Date Issue Change
28 September 2001 A First release of ARM7TDMI-S (Rev 4) processor
11 March 2004 B Second release
ARM DDI 0234B Copyright © 2001 ARM Limited. All rights reserved. iii
Contents
ARM7TDMI-S Technical Reference Manual
Preface
About this document ..................................................................................... xii
Feedback ..................................................................................................... xvi
Chapter 1 Introduction
1.1 About the ARM7TDMI-S processor ............................................................. 1-2
1.2 ARM7TDMI-S architecture .......................................................................... 1-4
1.3 ARM7TDMI-S block, core and functional diagrams .................................... 1-6
1.4 ARM7TDMI-S instruction set summary ....................................................... 1-9
1.5 Differences between Rev 3a and Rev 4 .................................................... 1-23
Chapter 2 Programmer’s Model
2.1 About the programmer’s model ................................................................... 2-2
2.2 Processor operating states ......................................................................... 2-3
2.3 Memory formats .......................................................................................... 2-4
2.4 Instruction length ......................................................................................... 2-6
2.5 Data types ................................................................................................... 2-7
2.6 Operating modes ........................................................................................ 2-8
2.7 Registers ..................................................................................................... 2-9
2.8 The program status registers .................................................................... 2-16
2.9 Exceptions ................................................................................................ 2-19
2.10 Interrupt latencies ..................................................................................... 2-26
Contents
iv Copyright © 2001 ARM Limited. All rights reserved. ARM DDI 0234B
2.11 Reset ........................................................................................................ 2-27
Chapter 3 Memory Interface
3.1 About the memory interface ....................................................................... 3-2
3.2 Bus interface signals .................................................................................. 3-3
3.3 Bus cycle types .......................................................................................... 3-4
3.4 Addressing signals ................................................................................... 3-10
3.5 Data timed signals .................................................................................... 3-13
3.6 Using CLKEN to control bus cycles .......................................................... 3-17
Chapter 4 Coprocessor Interface
4.1 About coprocessors .................................................................................... 4-2
4.2 Coprocessor interface signals .................................................................... 4-4
4.3 Pipeline-following signals ........................................................................... 4-5
4.4 Coprocessor interface handshaking ........................................................... 4-6
4.5 Connecting coprocessors ......................................................................... 4-11
4.6 Not using an external coprocessor .......................................................... 4-14
4.7 Undefined instructions .............................................................................. 4-15
4.8 Privileged instructions ............................................................................... 4-16
Chapter 5 Debugging Your System
5.1 About debugging your system .................................................................... 5-3
5.2 Controlling debugging ................................................................................. 5-5
5.3 Entry into debug state ................................................................................. 5-7
5.4 Debug interface ........................................................................................ 5-12
5.5 ARM7TDMI-S core clock domains ........................................................... 5-13
5.6 The EmbeddedICE-RT macrocell ............................................................. 5-14
5.7 Disabling EmbeddedICE-RT .................................................................... 5-16
5.8 EmbeddedICE-RT register map ............................................................... 5-17
5.9 Monitor mode debugging .......................................................................... 5-18
5.10 The debug communications channel ........................................................ 5-20
5.11 Scan chains and the JTAG interface ........................................................ 5-24
5.12 The TAP controller .................................................................................... 5-26
5.13 Public JTAG instructions .......................................................................... 5-28
5.14 Test data registers .................................................................................... 5-31
5.15 Scan timing ............................................................................................... 5-36
5.16 Examining the core and the system in debug state .................................. 5-39
5.17 Exit from debug state ................................................................................ 5-42
5.18 The program counter during debug .......................................................... 5-44
5.19 Priorities and exceptions .......................................................................... 5-47
5.20 Watchpoint unit registers .......................................................................... 5-48
5.21 Programming breakpoints ........................................................................ 5-53
5.22 Programming watchpoints ........................................................................ 5-55
5.23 Abort status register ................................................................................. 5-56
5.24 Debug control register .............................................................................. 5-57
5.25 Debug status register ............................................................................... 5-60
Contents
ARM DDI 0234B Copyright © 2001 ARM Limited. All rights reserved. v
5.26 Coupling breakpoints and watchpoints ..................................................... 5-62
5.27 EmbeddedICE-RT timing .......................................................................... 5-65
Chapter 6 ETM Interface
6.1 About the ETM interface ............................................................................. 6-2
6.2 Enabling and disabling the ETM7 interface ................................................. 6-3
6.3 ETM7 to ARM7TDMI-S (Rev 4) connections .............................................. 6-4
6.4 Clocks and resets ....................................................................................... 6-6
6.5 Debug request wiring .................................................................................. 6-7
Chapter 7 Instruction Cycle Timings
7.1 About the instruction cycle timings .............................................................. 7-3
7.2 Instruction cycle count summary ................................................................. 7-5
7.3 Branch and ARM branch with link ............................................................... 7-7
7.4 Thumb branch with link ............................................................................... 7-8
7.5 Branch and exchange ................................................................................. 7-9
7.6 Data operations ......................................................................................... 7-10
7.7 Multiply, and multiply accumulate ............................................................. 7-12
7.8 Load register ............................................................................................. 7-14
7.9 Store register ............................................................................................ 7-16
7.10 Load multiple registers .............................................................................. 7-17
7.11 Store multiple registers ............................................................................. 7-19
7.12 Data swap ................................................................................................. 7-20
7.13 Software interrupt, and exception entry .................................................... 7-21
7.14 Coprocessor data processing operation ................................................... 7-22
7.15 Load coprocessor register (from memory to coprocessor) ....................... 7-23
7.16 Store coprocessor register (from coprocessor to memory) ....................... 7-25
7.17 Coprocessor register transfer (move from coprocessor to ARM register) . 7-27
7.18 Coprocessor register transfer (move from ARM register to coprocessor) . 7-28
7.19 Undefined instructions and coprocessor absent ....................................... 7-29
7.20 Unexecuted instructions ............................................................................ 7-30
Chapter 8 AC Parameters
8.1 Timing diagrams ......................................................................................... 8-2
8.2 AC timing parameter definitions .................................................................. 8-8
Appendix A Signal Descriptions
A.1 Signal descriptions ...................................................................................... A-2
Appendix B Differences Between the ARM7TDMI-S and the ARM7TDMI
B.1 Interface signals .......................................................................................... B-2
B.2 ATPG scan interface ................................................................................... B-6
B.3 Timing parameters ...................................................................................... B-7
B.4 ARM7TDMI-S design considerations .......................................................... B-8
