jtd.rar_quartus交通灯

----------控制部件---------- library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; entity jtd_state is port(clk,clr:in std_logic; light:out std_logic_vector(5 downto 0); at,bt:out std_logic_vector(7 downto 0)); end jtd_state; architecture one of jtd_state is type state_type is (s0,s1,s2,s3); signal state:state_type; signal ati,bti:std_logic_vector(7 downto 0); signal lt:std_logic_vector(5 downto 0); signal red,gre,yel:std_logic_vector(7 downto 0); begin red<=x"30"; gre<=x"25"; yel<=x"05"; ----------状态机主控时序进程--------- process(clk,clr) begin if clr='1' then state<=s0; elsif(clk='1' and clk'event) if(ati=x"01") or (bti=x"01") then case state is when s0 => state<=s1; when s1 => state<=s2; when s2 => state<=s3; when s3 => state<=s0; when others => state<=s0; end case; end if; if ati/=x"01" then if ati(3 downto 0)="0000" then ati(3 downto 0)<="1001"; ati(7 downto 4)<=ati(7 downto4)-1; else ati(3 downto 0)<=ati(3 downto 0)-1; ati(7 downto 4)<=ati(7 downto4); end if; end if; if bti/=x"01" then if bti(3 downto 0)="0000" then bti(3 downto 0)<="1001"; bti(7 downto 4)<=bti(7 downto4)-1; else bti(3 downto 0)<=bti(3 downto 0)-1; bti(7 downto 4)<=bti(7 downto4); end if; end if; end if; end process; -----------状态机主控组合进程------ process(state) begin case state is when s0 => ati<=red;bti<=gre;lt<="100010"; ----------ared,agreen,ayellow,bred,bgreen,byellow when s1 => bti<=yel;lt<="100001"; when s2 => ati<=gre;bti<=red;lt<="010100"; when s3 => ati<=yel;lt<="001100"; end case; end process; light<=lt; at<=ati; bt<=bti; end one; ----------------数码管上显示jtd_dis --------------- library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; entity jtd_dis is port(clk1k,clr:in std_logic; at,bt:in std_logic_vector(7 downto 0); led:out std_logic_vector(6 downto 0); sel:out std_logic_vector(2 downto 0)); end jtd_dis; architecture two of jtd_dis is signal sl:std_logic_vector(2 downto 0); signal ou:std_logic_vector(3 downto 0); signal ds:std_logic_vector(7 downto 0); begin process(clk1k,clr) begin if (clr='1') then sl<="111"; elsif (clk1k='1' and clk1k'event) then if sl="101" then sl<="000"; else sl<=sl+1; end if; end if; end process; process(sl) begin case sl is when "000" => ou<=bt(3 downto 0); when "001" => ou<=bt(7 downto 4); when "010" => ou<=x"b"; when "100" => ou<=at(3 downto 0); when "101" => ou<=at(7 downto 4); when "110" => ou<=x"a"; when others => ou<=x"f"; end case; end process; process(ou); begin case ou is when x"0" => ds<=x"3f"; when x"1" => ds<=x"06"; when x"2" => ds<=x"5b"; when x"3" => ds<=x"4f"; when x"4" => ds<=x"66"; when x"5" => ds<=x"6d"; when x"6" => ds<=x"7d"; when x"7" => ds<=x"07"; when x"8" => ds<=x"7f"; when x"9" => ds<=x"6f"; when x"a" => ds<=x"77"; when x"b" => ds<=x"7c"; when others => ds<=x"00"; end case; end process; led<=ds; sel<=sl; end two; ----------顶层文件jtd------------ library ieee; use ieee.std_logic_1164.all; use ieee.std_ligic_unsigned.all; entity jtd is port( clk,clk1k,clr:in std_logic; led: out std_logic_vector(6 downto 0); sel: out std_logic_vector(2 downto 0); light: out std_logic_vector(5 downto 0)); end jtd; architecture bhv of jtd is component jtd_state port( clk,clr:in std_logic; at,bt:out std_logic_vector(7 downto 0); light:out std_logic_vector(5 downto 0)); end component; component jtd_dis port(clk1k,clr:in std_logic; at,bt:in std_logic_vector(7 downto 0); led:out std_logic_vector(6 downto 0); sel:out std_logic_vector(2 downto 0)); end component; signal a,b:std_logic_vector(7 downto 0); signal begin u1:jtd_state port map(clk=>clk;clr=>clr;at=>a;bt>=b;light=>light); u2:jtd_dis port map(clk1k=>clk1k;clr=>clr;at=>a;bt=>b;led=>led;sel=>sel); end bhv;