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LIBRARY IEEE; --分频器
USE ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
ENTITY Fenpin IS
PORT
( Clock: IN STD_LOGIC;
Clockout: OUT STD_LOGIC);
END Fenpin;
ARCHITECTURE bhv OF Fenpin IS
BEGIN
PROCESS(Clock)
VARIABLE cout:INTEGER RANGE 0 TO 1000;
BEGIN
IF Clock'EVENT AND Clock='1' THEN
cout:=cout+1;
IF cout=1000 THEN Clockout<='1';cout:=0;
ELSE Clockout<='0';
END IF;
END IF;
END PROCESS;
END ;
LIBRARY IEEE; --分频器
USE ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
ENTITY Fenpin1 IS
PORT
( Clock1: IN STD_LOGIC;
Clockout1: OUT STD_LOGIC);
END Fenpin1;
ARCHITECTURE bhv OF Fenpin1 IS
BEGIN
PROCESS(Clock1)
VARIABLE cout:INTEGER RANGE 0 TO 1000;
BEGIN
IF Clock1'EVENT AND Clock1='1' THEN
cout:=cout+1;
IF cout=1000 THEN Clockout1<='1';cout:=0;
ELSE Clockout1<='0';
END IF;
END IF;
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