guard_against_theft.rar_CPLD_Verilogphone_Xilinx

共186个文件

htm：67个

jpg：32个

gif：27个

版权申诉

cpld

xilinx

vhdl

98 浏览量 2022-09-23 08:21:12 上传评论收藏 897KB RAR 举报

资源详情

资源评论

资源推荐

收起资源包目录

guard_against_theft.rar_CPLD_Verilog phone_Xilinx_verilog xilinx （186个子文件）

main__ctrl.bin 13KB

main_ctrl.bld 590B

_impact.cmd 254B

main_ctrl.cmd_log 5KB

cpldta_style.css 4KB

toc.css 1003B

style.css 630B

main_ctrl_pad.csv 2KB

fang-dao.ddb 640KB

tmperr.err 0B

functionblock.gif 22KB

pindiagram.gif 21KB

equations.gif 20KB

fb.gif 11KB

xc9500xl_logo.gif 9KB

xc9500_logo.gif 8KB

fb1.gif 8KB

header.gif 8KB

macrocell.gif 8KB

errors1.gif 6KB

errors2.gif 4KB

xlogo.gif 3KB

pin.gif 3KB

view.gif 3KB

endmkt.gif 2KB

legend.gif 1KB

search.gif 975B

home.gif 940B

xcenter.gif 868B

products.gif 828B

education.gif 816B

support.gif 760B

contact.gif 741B

purchase.gif 642B

beginstraight.gif 352B

spacer.gif 233B

blank.gif 43B

main_ctrl.gyd 920B

timing_report.htm 91KB

eqns.htm 43KB

optionsdoc.htm 40KB

ascii.htm 29KB

fbs_FB1.htm 22KB

fbs_FB4.htm 20KB

defeqns.htm 18KB

pinsdoc.htm 15KB

fbs_FB2.htm 14KB

fbs_FBdoc.htm 14KB

cpldta_glossary.htm 13KB

fbs_FB3.htm 13KB

maplogic_02.htm 13KB

maplogic_00.htm 12KB

maplogic_01.htm 12KB

summarydoc.htm 8KB

pins.htm 8KB

maplogicdoc.htm 7KB

mapinputdoc.htm 6KB

pinlegendV.htm 5KB

summary.htm 5KB

logicleftdoc.htm 4KB

logiclegendV.htm 4KB

leftnav.htm 4KB

failtabledoc.htm 4KB

pinlegend.htm 4KB

fbsdoc.htm 4KB

inputleftdoc.htm 3KB

errorsdoc.htm 3KB

logiclegend.htm 3KB

options.htm 3KB

mapinput_00.htm 3KB

mapinput_01.htm 3KB

mapinput_02.htm 3KB

fbs.htm 2KB

asciidoc.htm 2KB

failtable.htm 2KB

unmaplogicdoc.htm 2KB

unmapinputdoc.htm 2KB

equationsdoc.htm 1KB

leftnav.htm 1KB

topnav.htm 1KB

logicleft.htm 996B

pin_legXbr.htm 948B

inputleft.htm 921B

errs.htm 864B

report.htm 766B

report.htm 674B

genreport.htm 674B

newappletref.htm 601B

index.htm 598B

appletref.htm 597B

logic_legXbr.htm 587B

pin_legXC95.htm 520B

pin_legXpla3.htm 507B

topnav.htm 473B

result.htm 354B

genmsg.htm 351B

checkNS4.htm 288B

check.htm 285B

equations.htm 239B

wait.htm 230B

共 186 条

<!DOCTYPE HTML PUBLIC "-//w3c//dtd html 4.0 transitional//en"> <HTML> <HEAD> <meta http-equiv="Content-Type" content="text/html; charset=UTF-8"> <meta name="Generator" content="Timing Report Generator: version I.27"> <meta name="Author" content="Copyright (c) 1995-2005 Xilinx, Inc. All rights reserved."> <meta name="Description" content="Timing report for main_ctrl"> <TITLE>Timing report for main_ctrl</TITLE> <script language="Javascript">  </script> </HEAD> <A NAME="Top"></a> <A NAME="TimingReport"></a><h1 ALIGN="center" CLASS="cpldta_text_report_header">Timing Report</h1> <CENTER><SPAN CLASS="cpldta_text_normal_bold"><A HREF="cpldta_glossary.htm"><B>Need help reading this report?</B></A></SPAN></CENTER><BR> <TABLE WIDTH="60%" border="1" ALIGN="center"> <TR> <TD WIDTH="35%" CLASS="cpldta_text_normal_bold"><B>Design Name</B></TD> <TD WIDTH="65%" CLASS="cpldta_text_normal">main_ctrl</TD> </TR> <TR> <TD WIDTH="35%" CLASS="cpldta_text_normal_bold"><B>Device, Speed (SpeedFile Version)</B></TD> <TD WIDTH="65%" CLASS="cpldta_text_normal"><A HREF="Javascript:popWin('http://www.xilinx.com/literature/index.htm','800','800','test');">XC9572XL</A>, -5 (3.0)</TD> </TR> <TR> <TD WIDTH="35%" CLASS="cpldta_text_normal_bold"><B>Date Created</B></TD> <TD WIDTH="65%" CLASS="cpldta_text_normal">Tue Nov 18 15:35:58 2008 </TD> </TR> <TR> <TD WIDTH="35%" CLASS="cpldta_text_normal_bold"><B>Created By</B></TD> <TD WIDTH="65%" CLASS="cpldta_text_normal">Timing Report Generator: version I.27</TD> </TR> <TR> <TD WIDTH="35%" CLASS="cpldta_text_normal_bold"><B>Copyright</B></TD> <TD WIDTH="65%" CLASS="cpldta_text_normal">Copyright (c) 1995-2005 Xilinx, Inc. All rights reserved.</TD> </TR> </TABLE> <A NAME="Summary"></a><h2 ALIGN="center" CLASS="cpldta_text_section_header">Summary</h2> <TABLE WIDTH="80%" border="1" ALIGN="center"> <TR CLASS="cpldta_warnings_header"> <TH BGCOLOR="#FFFFCC" WIDTH="100%">Notes and Warnings</TH> </TR> <TR> <TD WIDTH="100%" CLASS="cpldta_text_normal">Note: This design contains no timing constraints.</TD> </TR> <TR> <TD WIDTH="100%" CLASS="cpldta_text_normal">Note: A default set of constraints using a delay of 0.000ns will be used for analysis.</TD> </TR> </TABLE><BR> <TABLE WIDTH="80%" border="1" ALIGN="center"> <TR CLASS="cpldta_warnings_header"> <TH BGCOLOR="#FFFFCC" WIDTH="100%" colspan="2">Performance Summary</TH> </TR> <TR> <TD WIDTH="65%" CLASS="cpldta_text_normal_bold"><B>Min. Clock Period</B></TD> <TD WIDTH="35%" CLASS="cpldta_text_normal">6.600 ns.</TD> </TR> <TR> <TD WIDTH="65%" CLASS="cpldta_text_normal_bold"><B>Max. Clock Frequency </B><A HREF="cpldta_glossary.htm#fSYSTEM">(fSYSTEM)</A></TD> <TD WIDTH="35%" CLASS="cpldta_text_normal">151.515 MHz. </TD> </TR> <TR> <TD WIDTH="100%" colspan="2" CLASS="cpldta_text_normal">Limited by Cycle Time for clk5hz</TD> </TR> <TR> <TD WIDTH="65%" CLASS="cpldta_text_normal_bold"><B>Clock to Setup </B><A HREF="cpldta_glossary.htm#tCYC">(tCYC)</A></TD> <TD WIDTH="35%" CLASS="cpldta_text_normal">6.600 ns. </TD> </TR> <TR> <TD WIDTH="65%" CLASS="cpldta_text_normal_bold"><B>Pad to Pad Delay </B><A HREF="cpldta_glossary.htm#tPD">(tPD)</A></TD> <TD WIDTH="35%" CLASS="cpldta_text_normal">5.000 ns. </TD> </TR> <TR> <TD WIDTH="65%" CLASS="cpldta_text_normal_bold"><B>Setup to Clock at the Pad </B><A HREF="cpldta_glossary.htm#tSU">(tSU)</A></TD> <TD WIDTH="35%" CLASS="cpldta_text_normal">4.700 ns. </TD> </TR> <TR> <TD WIDTH="65%" CLASS="cpldta_text_normal_bold"><B>Clock Pad to Output Pad Delay </B><A HREF="cpldta_glossary.htm#tCO">(tCO)</A></TD> <TD WIDTH="35%" CLASS="cpldta_text_normal">8.900 ns. </TD> </TR> </TABLE> <HR> <A NAME="TimingConstraints"></a><h2 ALIGN="center" CLASS="cpldta_text_section_header">Timing Constraints</h2> <TABLE WIDTH="80%" border="1" ALIGN="center"> <TR> <TH BGCOLOR="#FFFFCC" CLASS="cpldta_constraint_header">Constraint Name</TH> <TH BGCOLOR="#FFFFCC" WIDTH="15%" CLASS="cpldta_time_header">Requirement (ns)</TH> <TH BGCOLOR="#FFFFCC" WIDTH="15%" CLASS="cpldta_time_header">Delay (ns)</TH> <TH BGCOLOR="#FFFFCC" WIDTH="15%" CLASS="cpldta_time_header">Paths</TH> <TH BGCOLOR="#FFFFCC" WIDTH="15%" CLASS="cpldta_time_header">Paths Failing</TH> </TR> <TR> <TD ALIGN="left" CLASS="cpldta_constraint_name"><A HREF="#TS1000">TS1000</A></TD> <TD ALIGN="center" CLASS="cpldta_time_value">0.0</TD> <TD ALIGN="center" CLASS="cpldta_time_value">0.0</TD> <TD ALIGN="center" CLASS="cpldta_time_value">0</TD> <TD ALIGN="center" CLASS="cpldta_time_value">0</TD> </TR> <TR> <TD BGCOLOR="#FFCCCC" ALIGN="left" CLASS="cpldta_constraint_name_error"><A HREF="#AUTO_TS_F2F">AUTO_TS_F2F</A></TD> <TD BGCOLOR="#FFCCCC" ALIGN="center" CLASS="cpldta_time_value_error">0.0</TD> <TD BGCOLOR="#FFCCCC" ALIGN="center" CLASS="cpldta_time_value_error">6.6</TD> <TD BGCOLOR="#FFCCCC" ALIGN="center" CLASS="cpldta_time_value_error">209</TD> <TD BGCOLOR="#FFCCCC" ALIGN="center" CLASS="cpldta_time_value_error">209</TD> </TR> <TR> <TD BGCOLOR="#FFCCCC" ALIGN="left" CLASS="cpldta_constraint_name_error"><A HREF="#AUTO_TS_P2P">AUTO_TS_P2P</A></TD> <TD BGCOLOR="#FFCCCC" ALIGN="center" CLASS="cpldta_time_value_error">0.0</TD> <TD BGCOLOR="#FFCCCC" ALIGN="center" CLASS="cpldta_time_value_error">8.9</TD> <TD BGCOLOR="#FFCCCC" ALIGN="center" CLASS="cpldta_time_value_error">8</TD> <TD BGCOLOR="#FFCCCC" ALIGN="center" CLASS="cpldta_time_value_error">8</TD> </TR> <TR> <TD BGCOLOR="#FFCCCC" ALIGN="left" CLASS="cpldta_constraint_name_error"><A HREF="#AUTO_TS_P2F">AUTO_TS_P2F</A></TD> <TD BGCOLOR="#FFCCCC" ALIGN="center" CLASS="cpldta_time_value_error">0.0</TD> <TD BGCOLOR="#FFCCCC" ALIGN="center" CLASS="cpldta_time_value_error">5.8</TD> <TD BGCOLOR="#FFCCCC" ALIGN="center" CLASS="cpldta_time_value_error">17</TD> <TD BGCOLOR="#FFCCCC" ALIGN="center" CLASS="cpldta_time_value_error">17</TD> </TR> <TR> <TD BGCOLOR="#FFCCCC" ALIGN="left" CLASS="cpldta_constraint_name_error"><A HREF="#AUTO_TS_F2P">AUTO_TS_F2P</A></TD> <TD BGCOLOR="#FFCCCC" ALIGN="center" CLASS="cpldta_time_value_error">0.0</TD> <TD BGCOLOR="#FFCCCC" ALIGN="center" CLASS="cpldta_time_value_error">7.8</TD> <TD BGCOLOR="#FFCCCC" ALIGN="center" CLASS="cpldta_time_value_error">5</TD> <TD BGCOLOR="#FFCCCC" ALIGN="center" CLASS="cpldta_time_value_error">5</TD> </TR> </TABLE> </BR> </BR> <A NAME="TS1000"> <h3 CLASS="cpldta_text_subsection_header">Constraint: TS1000</h3> <TABLE WIDTH="80%" border="1" ALIGN="center"> <CAPTION CLASS="cpldta_text_caption"><B>Description: PERIOD:PERIOD_clk5hz:0.000 nS</B></CAPTION> <TR CLASS="cpldta_delaytable_header"> <TH BGCOLOR="#FFFFCC" WIDTH="40%" CLASS="cpldta_constraint_header">Path</TH> <TH BGCOLOR="#FFFFCC" WIDTH="20%" CLASS="cpldta_time_header">Requirement (ns)</TH> <TH BGCOLOR="#FFFFCC" WIDTH="20%" CLASS="cpldta_time_header">Delay (ns)</TH> <TH BGCOLOR="#FFFFCC" WIDTH="20%" CLASS="cpldta_time_header">Slack (ns)</TH> </TR> </TABLE> </BR> </BR> <A NAME="AUTO_TS_F2F"> <h3 CLASS="cpldta_text_subsection_header">Constraint: AUTO_TS_F2F</h3> <TABLE WIDTH="80%" border="1" ALIGN="center"> <CAPTION CLASS="cpldta_text_caption"><B>Description: MAXDELAY:FROM:FFS(*):TO:FFS(*):0.000 nS</B></CAPTION> <TR CLASS="cpldta_delaytable_header"> <TH BGCOLOR="#FFFFCC" WIDTH="40%" CLASS="cpldta_constraint_header">Path</TH> <TH BGCOLOR="#FFFFCC" WIDTH="20%" CLASS="cpldta_time_header">Requirement (ns)</TH> <TH BGCOLOR="#FFFFCC" WIDTH="20%" CLASS="cpldta_time_header">Delay (ns)</TH> <TH BGCOLOR="#FFFFCC" WIDTH="20%" CLASS="cpldta_time_header">Slack (ns)</TH> </TR> <TR> <A NAME="_state_0__Q_to_led1_D"></A>