LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
use ieee.std_logic_unsigned.all;
ENTITY ad9851 is
port(reset:buffer std_logic;
clk:in std_logic;
data:out std_logic_vector(7 downto 0);
wclk:out std_logic;
fqud:out std_logic);
end ad9851;
architecture state of ad9851 is
signal w0,w1,w2,w3,w4:std_logic_vector(7 downto 0);
signal temp:std_logic_vector(4 downto 0):="00000";
begin
reset<='0';
w0<="00001000";
w1<="00101010";
w2<="10101010";
w3<="10101010";
w4<="10101010";--3MHZ
process(clk,temp)
begin
if(reset='1') then
temp<="00000";
elsif (clk'event and clk='1') then
if temp <"10101" then
temp<=temp+1;
else
temp<=temp;
fqud <= temp(4)and temp(2) and temp(0);
wclk<='0';
end if;
end if;
wclk <= temp(1);
end process;
process(temp,clk)
begin
IF RISING_EDGE(clk) THEN
case temp is
when "00000"=>data<=w0;
when "00001"=>data<=w0;
when "00010"=>data<=w0;
when "00011"=>data<=w1;
when "00100"=>data<=w1;
when "00101"=>data<=w1;
when "00110"=>data<=w1;
when "00111"=>data<=w2;
when "01000"=>data<=w2;
when "01001"=>data<=w2;
when "01010"=>data<=w2;
when "01011"=>data<=w3;
when "01100"=>data<=w3;
when "01101"=>data<=w3;
when "01110"=>data<=w3;
when "01111"=>data<=w4;
when "10000"=>data<=w4;
when "10001"=>data<=w4;
when "10010"=>data<=w4;
when "10011"=>data<=w4;
when others=>null;
end case;
END IF;
end process;
end state;
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