dds_vhdl.rar_DDS_VHDL_vhdl fpga_正弦扫频_正弦波_正弦波 FPGA

Release 10.1 - par K.31 (nt) Copyright (c) 1995-2008 Xilinx, Inc. All rights reserved. Sun Aug 23 14:51:23 2009 INFO: The IO information is provided in three file formats as part of the Place and Route (PAR) process. These formats are: 1. The <design name>_pad.txt file (this file) designed to provide information on IO usage in a human readable ASCII text format viewable through common text editors. 2. The <design namd>_pad.csv file for use with spreadsheet programs such as MS Excel. This file can also be read by PACE to communicate post PAR IO information. 3. The <design name>.pad file designed for parsing by customers. It uses the "|" as a data field separator. INPUT FILE: dds_map.ncd OUTPUT FILE: dds_pad.txt PART TYPE: xc3s200 SPEED GRADE: -5 PACKAGE: ft256 Pinout by Pin Number: +--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ |Pin Number|Signal Name |Pin Usage|Pin Name |Direction|IO Standard|IO Bank Number|Drive (mA)|Slew Rate|Termination|IOB Delay|Voltage |Constraint|DCI Value|IO Register|Signal Integrity| +--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ |A1 | | |GND | | | | | | | | | | | | | |A2 | | |TDI | | | | | | | | | | | | | |A3 | |IOB |IO/VREF_0 |UNUSED | |0 | | | | | | | | | | |A4 | |DIFFM |IO_L01P_0/VRN_0 |UNUSED | |0 | | | | | | | | | | |A5 |dds_fdata<11>|IOB |IO |OUTPUT |LVCMOS25* |0 |12 |SLOW |NONE** | | | | |NO |NONE | |A6 | | |VCCAUX | | | | | | | |2.5 | | | | | |A7 |dds_data<4> |IOB |IO |OUTPUT |LVCMOS25* |0 |12 |SLOW |NONE** | | | | |NO |NONE | |A8 |dds_data<0> |IOB |IO_L32P_0/GCLK6 |OUTPUT |LVCMOS25* |0 |12 |SLOW |NONE** | | | | |NO |NONE | |A9 |dds_data<3> |IOB |IO |OUTPUT |LVCMOS25* |1 |12 |SLOW |NONE** | | | | |NO |NONE | |A10 |channel<1> |IOB |IO_L31N_1/VREF_1 |INPUT |LVCMOS25* |1 | | | |NONE | | | |NO |NONE | |A11 | | |VCCAUX | | | | | | | |2.5 | | | | | |A12 | |IOB |IO |UNUSED | |1 | | | | | | | | | | |A13 | |DIFFS |IO_L10N_1/VREF_1 |UNUSED | |1 | | | | | | | | | | |A14 | |DIFFS |IO_L01N_1/VRP_1 |UNUSED | |1 | | | | | | | | | | |A15 | | |TDO | | | | | | | | | | | | | |A16 | | |GND | | | | | | | | | | | | | |B1 | |DIFFM |IO_L01P_7/VRN_7 |UNUSED | |7 | | | | | | | | | | |B2 | | |GND | | | | | | | | | | | | | |B3 | | |PROG_B | | | | | | | | | | | | | |B4 | |DIFFS |IO_L01N_0/VRP_0 |UNUSED | |0 | | | | | | | | | | |B5 |dds_fdata<6> |IOB |IO_L25P_0 |OUTPUT |LVCMOS25* |0 |12 |SLOW |NONE** | | | | |NO |NONE | |B6 |dds_fdata<1> |IOB |IO_L28P_0 |OUTPUT |LVCMOS25* |0 |12 |SLOW |NONE** | | | | |NO |NONE | |B7 |dds_data<5> |IOB |IO_L30P_0 |OUTPUT |LVCMOS25* |0 |12 |SLOW |NONE** | | | | |NO |NONE | |B8 |dds_data<1> |IOB |IO_L32N_0/GCLK7 |OUTPUT |LVCMOS25* |0 |12 |SLOW |NONE** | | | | |NO |NONE | |B9 | | |GND | | | | | | | | | | | | | |B10 |channel<0> |IOB |IO_L31P_1 |INPUT |LVCMOS25* |1 | | | |NONE | | | |NO |NONE | |B11 | |DIFFS |IO_L29N_1 |UNUSED | |1 | | | | | | | | | | |B12 | |DIFFS |IO_L27N_1 |UNUSED | |1 | | | | | | | | | | |B13 | |DIFFM |IO_L10P_1 |UNUSED | |1 | | | | | | | | | | |B14 | |DIFFM |IO_L01P_1/VRN_1 |UNUSED | |1 | | | | | | | | | | |B15 | | |GND | | | | | | | | | | | | | |B16 | |DIFFS |IO_L01N_2/VRP_2 |UNUSED | |2 | | | | | | | | | | |C1 | |DIFFS |IO_L01N_7/VRP_7 |UNUSED | |7 | | | | | | | | | | |C2 | |DIFFS |IO_L16N_7 |UNUSED |