+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Legal Partition Candidates ;
+--------------------------------------------+-------+----------------+--------------+----------------+--------+-----------------+---------------+-----------------+-------+----------------+--------------+------------------+-------------------+
; Hierarchy ; Input ; Constant Input ; Unused Input ; Floating Input ; Output ; Constant Output ; Unused Output ; Floating Output ; Bidir ; Constant Bidir ; Unused Bidir ; Input only Bidir ; Output only Bidir ;
+--------------------------------------------+-------+----------------+--------------+----------------+--------+-----------------+---------------+-----------------+-------+----------------+--------------+------------------+-------------------+
; mypll_inst|altpll_component|auto_generated ; 3 ; 0 ; 0 ; 0 ; 6 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ;
; mypll_inst ; 2 ; 0 ; 0 ; 0 ; 3 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ;
+--------------------------------------------+-------+----------------+--------------+----------------+--------+-----------------+---------------+-----------------+-------+----------------+--------------+------------------+-------------------+
PLL.zip_IP核_PLL_quartus II _verilog hdl_锁相
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2022-09-20
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PLL.zip_IP核_PLL_quartus II _verilog hdl_锁相 （102个子文件） 
_info 2KB _vmake 26B pll.map.ammdb 122B pll_run_msim_rtl_verilog.do.bak 645B pll_run_msim_rtl_verilog.do.bak1 645B pll_run_msim_rtl_verilog.do.bak2 645B pll_run_msim_rtl_verilog.do.bak3 645B pll.map.bpm 709B pll.rtlv_sg.cdb 4KB pll.rtlv_sg_swap.cdb 3KB pll.map.cdb 3KB pll.root_partition.map.cdb 3KB pll.sgdiff.cdb 3KB pll.root_partition.map.hbdb.cdb 2KB pll.(1).cnf.cdb 2KB pll.map_bb.cdb 2KB pll.(2).cnf.cdb 2KB pll.(3).cnf.cdb 2KB pll.(0).cnf.cdb 993B pll.root_partition.map.reg_db.cdb 193B _primary.dat 4KB _primary.dat 2KB _primary.dat 436B _primary.dat 315B logic_util_heursitic.dat 0B pll.db_info 139B pll.db_info 139B _primary.dbs 2KB _primary.dbs 2KB _primary.dbs 730B _primary.dbs 441B pll.pti_db_list.ddb 176B pll.tis_db_list.ddb 176B pll_run_msim_rtl_verilog.do 645B pll.done 26B pll.root_partition.map.dpi 4KB pll.root_partition.map.hbdb.hb_info 48B pll.pre_map.hdb 19KB pll.rtlv.hdb 16KB pll.sgdiff.hdb 15KB pll.map.hdb 11KB pll.root_partition.map.hdb 11KB pll.root_partition.map.hbdb.hdb 11KB pll.map_bb.hdb 10KB pll.(1).cnf.hdb 1KB pll.(2).cnf.hdb 1KB pll.(3).cnf.hdb 982B pll.(0).cnf.hdb 699B pll.hier_info 2KB pll.hif 3KB
pll.lpc.html 814B modelsim.ini 11KB pll.ipinfo 288B pll.root_partition.map.kpt 351B pll.map.kpt 348B pll.cmp_merge.kpt 208B pll.map_bb.logdb 4B pll.map.logdb 4B msim_transcript 2KB mypll.ppf 545B verilog.prw 2KB verilog.prw 1KB verilog.prw 395B verilog.prw 71B verilog.psm 32KB verilog.psm 16KB verilog.psm 5KB verilog.psm 3KB mypll.qip 444B mypll.qip 0B pll.map.qmsg 20KB pll.qpf 1KB pll.qsf 3KB pll.qws 674B pll.cmp.rdb 9KB pll.map.rdb 1KB pll.lpc.rdb 486B README 653B pll.map.rpt 65KB pll.flow.rpt 8KB pll_nativelink_simulation.rpt 957B pll.sld_design_entry_dsc.sci 201B pll.sld_design_entry.sci 201B pll.root_partition.map.hbdb.sig 32B pll.map.summary 454B pll.syn_hier_info 0B pll.tmw_info 58B
pll.lpc.txt 2KB cbx_args.txt 1KB pll.smart_action.txt 5B mypll.v 16KB mypll_bb.v 12KB mypll_altpll.v 5KB pll_tb.v 336B pll.v 230B mypll_inst.v 138B _primary.vhd 310B _primary.vhd 301B _primary.vhd 297B _primary.vhd 72B共 102 条
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