emac_loopback.rar_EMAC_EMAC loopback_dsp 以太网_emac_loopback

/* * Copyright 2007 by Spectrum Digital Incorporated. * All rights reserved. Property of Spectrum Digital Incorporated. */ /* * EMAC Test ( GMII mode ) * */ #include "emac.h" #define TX_BUF 128 #define RX_BUF 128 static Uint8 packet_data[TX_BUF]; static Uint8 packet_buffer1[RX_BUF]; static Uint8 packet_buffer2[RX_BUF]; static Uint8 packet_buffer3[RX_BUF]; static Uint8 packet_buffer4[RX_BUF]; static Uint8 packet_buffer5[RX_BUF]; static Uint8 packet_buffer6[RX_BUF]; static Uint8 packet_buffer7[RX_BUF]; static Uint8 packet_buffer8[RX_BUF]; static Uint8 packet_buffer9[RX_BUF]; static Uint8 packet_buffer10[RX_BUF]; /* * We use pDescBase for a base address. Its easier this way * because we can use indexing off the pointer. */ static EMAC_Desc* pDescBase = ( EMAC_Desc* )EMAC_RAM_BASE; /* * The following are used to allow the ISR to communicate with * the application. */ extern volatile Int32 RxCount; extern volatile Int32 TxCount; extern volatile Int32 ErrCount; extern volatile EMAC_Desc *pDescRx; extern volatile EMAC_Desc *pDescTx; /* ------------------------------------------------------------------------ * * gmii_phy_getReg( phynum, regnum ) * * ------------------------------------------------------------------------ */ Uint16 gmii_phy_getReg( Int16 phynum, Int16 regnum ) { Uint16 value; MDIO_USERACCESS0 = 0 // Read Phy Id 1 | ( 1 << 31 ) // [31] Go | ( 0 << 30 ) // [30] Read | ( 0 << 29 ) // [29] Ack | ( regnum << 21 ) // [25-21] PHY register address | ( phynum << 16 ) // [20-16] PHY address | ( 0 << 0 ); // [15-0] Data while( MDIO_USERACCESS0 & 0x80000000 ); // Wait for Results value = MDIO_USERACCESS0; return value; } /* ------------------------------------------------------------------------ * * gmii_phy_setReg( phynum, regnum, data ) * * ------------------------------------------------------------------------ */ void gmii_phy_setReg( Int16 phynum, Int16 regnum, Uint16 data ) { MDIO_USERACCESS0 = 0 // Read Phy Id 1 | ( 1 << 31 ) // [31] Go | ( 1 << 30 ) // [30] Write | ( 0 << 29 ) // [29] Ack | ( regnum << 21 ) // [25-21] PHY register address | ( phynum << 16 ) // [20-16] PHY address | ( data << 0 ); // [15-0] Data while( MDIO_USERACCESS0 & 0x80000000 ); // Wait for Results _waitusec( 1000 ); } /* ------------------------------------------------------------------------ * * gmii_phy_dumpRegs( ) * * ------------------------------------------------------------------------ */ void gmii_phy_dumpRegs( ) { Int16 i; for ( i = 0 ; i < 32 ; i++ ) printf( "PHY[%d] = %04x\n", i, gmii_phy_getReg( 1, i ) ); printf( "\n\n" ); } /* ------------------------------------------------------------------------ * * emac_gmii_init( ) * * ------------------------------------------------------------------------ */ Int16 emac_gmii_init( ) { Int16 i; volatile Uint32* pReg; /* 0. Reset Ethernet */ EMAC_SOFTRESET = 1; while( EMAC_SOFTRESET != 0 ); _waitusec( 100 ); /* ---------------------------------------------------------------- * * Init PHY / MDIO * * ---------------------------------------------------------------- */ MDIO_CONTROL = 0x40000020; // Enable MII interface ( MDIOCLK < 12.5MHz ) _waitusec( 100000 ); gmii_phy_setReg( 1, 0, 0xc140 ); // Force 1000mpbs, full duplex gmii_phy_setReg( 1, 28, 0x74f0 ); // Enable LINK LED for link, RXTX LED for TX/RX activity gmii_phy_setReg( 1, 22, 0x1012 ); // Enable SYS_CLK / GMII ( GTX_CLK ) printf( " In GMII mode\n" ); /* Reset Ethernet */ EMAC_SOFTRESET = 1; while( EMAC_SOFTRESET != 0 ); _waitusec( 100 ); MDIO_CONTROL = 0x40000020; // Enable MII interface ( MDIOCLK < 12.5MHz ) _waitusec( 100000 ); /* Gigabit PHY external cable loopback */ gmii_phy_setReg( 1, 19, 0x0080 ); // Enable cable loopback gmii_phy_setReg( 1, 0, 0x0140 ); // Force 1000mbps, full duplex /* Wait for link */ printf( " Waiting for link...\n" ); while( ( gmii_phy_getReg( 1, 1 ) & 0x04 ) == 0 ); printf( " Link Detected\n" ); //gmii_phy_dumpRegs( ); /* ---------------------------------------------------------------- * * Init EMAC * * ---------------------------------------------------------------- */ /* 1. Disable RX/TX interrupts */ EMAC_EWRXEN = 0x00000000; EMAC_EWTXEN = 0x00000000; /* 2. Clear the MAC control, receive control, & transmit control */ EMAC_MACCONTROL = 0; EMAC_RXCONTROL = 0; EMAC_TXCONTROL = 0; /* 3. Initialize all 16 header descriptor pointers RXnHDP & TXnHDP to zero */ EMAC_RX0HDP = 0; EMAC_RX1HDP = 0; EMAC_RX2HDP = 0; EMAC_RX3HDP = 0; EMAC_RX4HDP = 0; EMAC_RX5HDP = 0; EMAC_RX6HDP = 0; EMAC_RX7HDP = 0; EMAC_TX0HDP = 0; EMAC_TX1HDP = 0; EMAC_TX2HDP = 0; EMAC_TX3HDP = 0; EMAC_TX4HDP = 0; EMAC_TX5HDP = 0; EMAC_TX6HDP = 0; EMAC_TX7HDP = 0; /* 4. Clear all 36 statistics registers by writing 0 */ pReg = &EMAC_RXGOODFRAMES; for ( i = 0 ; i < 36 ; i++ ) *pReg++ = 0; /* 5. Setup the local Ethernet MAC address. Be sure to program all 8 MAC addresses */ EMAC_MACINDEX = 0x00; EMAC_MACADDRHI = 0x03020100; // Needs to be written only the first time EMAC_MACADDRLO = 0x0504; EMAC_MACINDEX = 0x01; EMAC_MACADDRLO = 0x1504; EMAC_MACINDEX = 0x02; EMAC_MACADDRLO = 0x2504; EMAC_MACINDEX = 0x03; EMAC_MACADDRLO = 0x3504; EMAC_MACINDEX = 0x04; EMAC_MACADDRLO = 0x4504; EMAC_MACINDEX = 0x05; EMAC_MACADDRLO = 0x5504; EMAC_MACINDEX = 0x06; EMAC_MACADDRLO = 0x6504; EMAC_MACINDEX = 0x07; EMAC_MACADDRLO = 0x7504; /* 6. Initialize the receive channel N */ /* 7. No multicast addressing */ EMAC_MACHASH1 = 0; EMAC_MACHASH2 = 0; /* 8. Set RX buffer offset to 0. Valid data always begins on the 1st byte */ EMAC_RXBUFFEROFFSET = 0; /* 9. Enable Unicast RX on channel 0-7 */ EMAC_RXUNICASTSET = 0xFF; /* 10. Setup the RX( M )ulticast ( B )roadcast ( P )romiscuous channel */ /* Enable multi-cast, broadcast and frames with errors */ EMAC_RXMBPENABLE = 0x01e02020; /* 11. Set the appropriate configuration bits in MACCONTROL (do not set the GMIIEN bit yet). */ EMAC_MACCONTROL = 0 | ( 0 << 9 ) // Round robin | ( 1 << 7 ) // Gigabit mode | ( 0 << 6 ) // TX pacing disabled | ( 0 << 5 ) // GMII RX & TX | ( 0 << 4 ) // TX flow disabled | ( 0 << 3 ) // RX flow disabled | ( 0 << 1 ) // Loopback disabled | ( 1 << 0 ); // full duplex /* 12. Clear all unused channel interrupt bits */ EMAC_RXINTMASKCLEAR = 0xFF; EMAC_TXINTMASKCLEAR = 0xFF; /* 13. Enable the RX & TX channel interrupt bits. */ EMAC_RXINTMASKSET = 0xFF; EMAC_TXINTMASKSET = 0xFF; /* Enable Host Error and Statistics interrupts */ EMAC_MACINTMASKSET = 0