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Synopsys, Inc.
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www.synopsys.com
2 Synopsys, Inc. September 2010
DesignWare DW_apb_rtc Databook
September 2010 Synopsys, Inc. 9
DesignWare DW_apb_rtc Databook Product Overview
SolvNet
DesignWare.com
1
Product Overview
The DW_apb_rtc is a programmable Real Time Clock (RTC) peripheral. This component is an AMBA
2.0-compliant Advanced Peripheral Bus (APB) slave device and is part of the family of DesignWare
Synthesizable Components.
1.1 DesignWare System Overview
The Synopsys DesignWare Synthesizable Components environment is a parameterizable bus system
containing AMBA version 2.0-compliant AHB (Advanced High-performance Bus) and APB (Advanced
Peripheral Bus) components, and AMBA version 3.0-compliant AXI (Advanced eXtensible Interface)
components.
Figure 1-1 illustrates one example of this environment, including the AXI bus, the AHB bus, and the APB
bus. Included in this subsystem are synthesizable IP for AXI/AHB/APB peripherals, bus bridges, and an
AXI interconnect and AHB bus fabric. Also included are verification IP for AXI/AHB/APB master/slave
models and bus monitors. In order to display the databook for a DW_* component, click on the
corresponding component object in the illustration.
Attention
10 Synopsys, Inc. September 2010
Product Overview DesignWare DW_apb_rtc Databook
SolvNet
DesignWare.com
Figure 1-1 Example of DW_apb_rtc in a Complete System
apb_monitor_vmt
DW_ahb (2)
DW_ahb_icm
DW_ahb_h2h,
DW_ahb_eh2h
Application-
Specific
Third-party
Peripherals
Logic
Application-
Specific
Logic
High-speed
USB, Ethernet,
PCI-X, and so on
Peripherals
DW_ahb
DW_ahb
Arbitration,
Decode, & Mux
Third-party
Peripherals
DW_ahb_dmac
APB Slave
VIP
AHB
VIP
Master/Slave
Third-party
Master
Third-party
Slave
DW_axi_gm DW_axi_gs
DW_ahb
DW_axi
Arbitration,
Decode, & Mux
axi_monitor_vmt
– Synopsys components – 3rd-party components
Third-party
Master/Slave
DW_axi_rs
Third-party
Master/Slave
AXI
VIP
Master/Slave
DW_ahb_eh2h
DW_axi_hmx
DW_axi_x2p
AMBA 3 Bridge
DW_apb_uart DW_apb_i2c
…
ahb_monitor_vmt
DW_memctl DW_ahb_dmacDW_ahb_ictl
RAM
Memory Models
DW_axi_x2h
Third-party
Slave
DW_axi_x2x
AMBA 3 Bridge
DW_ahb
DW_apb AHB/APB Bridge
DW_apb_ictl
DW_apb_rtc
DW_apb_uart
DW_apb_ssi
DW_apb_rap DW_apb_timers
DW_apb_wdtDW_apb_gpio
DW_apb_i2c
DW_apb_i2s
September 2010 Synopsys, Inc. 11
DesignWare DW_apb_rtc Databook Product Overview
SolvNet
DesignWare.com
1.2 General Product Description
The Synopsys DW_apb_rtc is a component of the DesignWare Advanced Peripheral Bus (DW_apb) and
conforms to the AMBA Specification, Revision 2.0 from ARM.
1.2.1 DW_apb_rtc Block Diagram
Figure 1-2 shows a block diagram of the DW_apb_rtc.
Figure 1-2 DW_apb_rtc Block Diagram
1.3 Features
DW_apb_rtc has the following features:
❖ APB slave interface with read/write coherency for registers
❖ Incrementing counter and comparator for interrupt generation
❖ Free-running pclk
❖ User-defined parameters:
✦ APB data bus width
✦ Counter width
✦ Clock relationship between bus clock and counter clock
✦ Interrupt polarity level
✦ Interrupt clock domain location
✦ Counter enable mode
✦ Counter wrap mode
DW_apb_rtc
APB
Interface
Synchronization
Counter
Register
Block
Read/Write
Coherency
Interrupt Generation
Up Counter
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