`timescale 1ns / 1ns
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 08:24:41 11/29/2012
// Design Name:
// Module Name: ad2s1205
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
//`define uu 1
module resolver01(
output data_out,
// input sclk,
output clk_out,
output cs,
// input data_in,
output fs1,
output fs2,
output reset,
output sample,
output rdvel // input clk_20M
);
//reg data_out;
//reg clk_out;
//reg cs;
//reg fs1;
//reg fs2;
//reg reset;
//reg sample;
//reg rdvel;
//reg [6:0]cnt20M;
//initial
//begin
//data_out=1;//给每个reg赋初值
//clk_out=0; //旋变的时钟输入空闲时候为低电平
//cs=0; //初始值cs使能,上电时可读
//cnt20M=7'b0000000;
//fs1=1;
//fs2=1;
//reset=1;
//sample=0;
//rdvel=0;
//end
//always @ ( negedge clk_20M )
// begin
// if (cnt20M==100)
// begin
// cnt20M<=0;
// reset<=1;
// end
// else
//begin
//cnt20M<=cnt20M+1;
//end
assign data_out=1,
clk_out=1, //旋变的时钟输入空闲时候为低电平
cs=1,//初始值cs使能,上电时可读
fs1=1,
fs2=1,
reset=1,sample=0,
rdvel=0;
//end
endmodule
#PACE: Start of Constraints generated by PACE
#PACE: Start of PACE I/O Pin Assignments
#NET "clk_20M" LOC = "P7" ;
NET "clk_out" LOC = "P35" ;
NET "cs" LOC = "P34" ;
#NET "data_in" LOC = "P33" ;
NET "data_out" LOC = "P42" ;
NET "fs1" LOC = "P29" ;
NET "fs2" LOC = "P28" ;
NET "rdvel" LOC = "P22" ;
NET "reset" LOC = "P27" ;
NET "sample" LOC = "P26" ;
#NET "sclk" LOC = "P39" ;
#PACE: Start of PACE Area Constraints
#PACE: Start of PACE Prohibit Constraints
#PACE: End of Constraints generated by PACE
`timescale 1ns /1ns
////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 08:32:14 11/29/2012
// Design Name: resolver01
// Module Name: D:/cpld/resolver20121129/test.v
// Project Name: resolver20121129
// Target Device:
// Tool versions:
// Description:
//
// Verilog Test Fixture created by ISE for module: resolver01
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module test;
// Inputs
// reg sclk;
// reg data_in;
//reg clk_20M;
// Outputs
wire data_out;
wire clk_out;
wire cs;
wire fs1;
wire fs2;
wire reset;
wire sample;
wire rdvel;
// Instantiate the Unit Under Test (UUT)
resolver01 uut (
.data_out(data_out),
//.sclk(sclk),
.clk_out(clk_out),
.cs(cs),
//.data_in(data_in),
.fs1(fs1),
.fs2(fs2),
.reset(reset),
.sample(sample),
.rdvel(rdvel)
//.clk_20M(clk_20M)
);
//always #25 clk_20M=~clk_20M;
//initial begin
// Initialize Inputs
// sclk = 0;
// data_in = 0;
// Wait 100 ns for global reset to finish
//#10000;
// Add stimulus here
//end
endmodule