EEPROM.rar_LPC EEPROM

/****************************************************************************** * @file: system_LPC177x_8x.c * @purpose: CMSIS Cortex-M3 Device Peripheral Access Layer Source File * for the NXP LPC177x_8x Device Series * @version: V1.1 * @date: 18th May 2009 *---------------------------------------------------------------------------- * * Copyright (C) 2008 ARM Limited. All rights reserved. * * ARM Limited (ARM) is supplying this software for use with Cortex-M3 * processor based microcontrollers. This file can be freely distributed * within development tools that are supporting such ARM based processors. * * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. * ******************************************************************************/ #include <stdint.h> #include "LPC177x_8x.h" /* //-------- <<< Use Configuration Wizard in Context Menu >>> ------------------ */ /*--------------------- Clock Configuration ---------------------------------- // // <e> Clock Configuration // <h> System Controls and Status Register (SCS) // <o1.4> OSCRANGE: Main Oscillator Range Select // <0=> 1 MHz to 20 MHz // <1=> 15 MHz to 24 MHz // <e1.5> OSCEN: Main Oscillator Enable // </e> // </h> // // <h> Clock Source Select Register (CLKSRCSEL) // <o2.0..1> CLKSRC: PLL Clock Source Selection // <0=> Internal RC oscillator // <1=> Main oscillator // <2=> RTC oscillator // </h> // // <e3> PLL0 Configuration (Main PLL) // <h> PLL0 Configuration Register (PLL0CFG) // <i> F_cco0 = (2 * M * F_in) / N // <i> F_in must be in the range of 32 kHz to 50 MHz // <i> F_cco0 must be in the range of 275 MHz to 550 MHz // <o4.0..14> MSEL: PLL Multiplier Selection // <6-32768><#-1> // <i> M Value // <o4.16..23> NSEL: PLL Divider Selection // <1-256><#-1> // <i> N Value // </h> // </e> // // <e5> PLL1 Configuration (USB PLL) // <h> PLL1 Configuration Register (PLL1CFG) // <i> F_usb = M * F_osc or F_usb = F_cco1 / (2 * P) // <i> F_cco1 = F_osc * M * 2 * P // <i> F_cco1 must be in the range of 156 MHz to 320 MHz // <o6.0..4> MSEL: PLL Multiplier Selection // <1-32><#-1> // <i> M Value (for USB maximum value is 4) // <o6.5..6> PSEL: PLL Divider Selection // <0=> 1 // <1=> 2 // <2=> 4 // <3=> 8 // <i> P Value // </h> // </e> // // <h> CPU Clock Configuration Register (CCLKSEL) // <o7.0..7> CCLKSEL: Divide Value for CPU Clock from PLL0 // <3-256><#-1> // </h> // // <h> USB Clock Configuration Register (USBSEL) // <o8.0..3> USBSEL: Divide Value for USB Clock from PLL1 // <0-15> // <i> Divide is USBSEL + 1 // </h> // // <h> Peripheral Clock Selection Register 0 (PCLKSEL0) // <o9.0..1> PCLK_WDT: Peripheral Clock Selection for WDT // <0=> Pclk = Cclk / 4 // <1=> Pclk = Cclk // <2=> Pclk = Cclk / 2 // <3=> Pclk = Hclk / 8 // <o9.2..3> PCLK_TIMER0: Peripheral Clock Selection for TIMER0 // <0=> Pclk = Cclk / 4 // <1=> Pclk = Cclk // <2=> Pclk = Cclk / 2 // <3=> Pclk = Hclk / 8 // <o9.4..5> PCLK_TIMER1: Peripheral Clock Selection for TIMER1 // <0=> Pclk = Cclk / 4 // <1=> Pclk = Cclk // <2=> Pclk = Cclk / 2 // <3=> Pclk = Hclk / 8 // <o9.6..7> PCLK_UART0: Peripheral Clock Selection for UART0 // <0=> Pclk = Cclk / 4 // <1=> Pclk = Cclk // <2=> Pclk = Cclk / 2 // <3=> Pclk = Hclk / 8 // <o9.8..9> PCLK_UART1: Peripheral Clock Selection for UART1 // <0=> Pclk = Cclk / 4 // <1=> Pclk = Cclk // <2=> Pclk = Cclk / 2 // <3=> Pclk = Hclk / 8 // <o9.12..13> PCLK_PWM1: Peripheral Clock Selection for PWM1 // <0=> Pclk = Cclk / 4 // <1=> Pclk = Cclk // <2=> Pclk = Cclk / 2 // <3=> Pclk = Hclk / 8 // <o9.14..15> PCLK_I2C0: Peripheral Clock Selection for I2C0 // <0=> Pclk = Cclk / 4 // <1=> Pclk = Cclk // <2=> Pclk = Cclk / 2 // <3=> Pclk = Hclk / 8 // <o9.16..17> PCLK_SPI: Peripheral Clock Selection for SPI // <0=> Pclk = Cclk / 4 // <1=> Pclk = Cclk // <2=> Pclk = Cclk / 2 // <3=> Pclk = Hclk / 8 // <o9.20..21> PCLK_SSP1: Peripheral Clock Selection for SSP1 // <0=> Pclk = Cclk / 4 // <1=> Pclk = Cclk // <2=> Pclk = Cclk / 2 // <3=> Pclk = Hclk / 8 // <o9.22..23> PCLK_DAC: Peripheral Clock Selection for DAC // <0=> Pclk = Cclk / 4 // <1=> Pclk = Cclk // <2=> Pclk = Cclk / 2 // <3=> Pclk = Hclk / 8 // <o9.24..25> PCLK_ADC: Peripheral Clock Selection for ADC // <0=> Pclk = Cclk / 4 // <1=> Pclk = Cclk // <2=> Pclk = Cclk / 2 // <3=> Pclk = Hclk / 8 // <o9.26..27> PCLK_CAN1: Peripheral Clock Selection for CAN1 // <0=> Pclk = Cclk / 4 // <1=> Pclk = Cclk // <2=> Pclk = Cclk / 2 // <3=> Pclk = Hclk / 6 // <o9.28..29> PCLK_CAN2: Peripheral Clock Selection for CAN2 // <0=> Pclk = Cclk / 4 // <1=> Pclk = Cclk // <2=> Pclk = Cclk / 2 // <3=> Pclk = Hclk / 6 // <o9.30..31> PCLK_ACF: Peripheral Clock Selection for ACF // <0=> Pclk = Cclk / 4 // <1=> Pclk = Cclk // <2=> Pclk = Cclk / 2 // <3=> Pclk = Hclk / 6 // </h> // // <h> Peripheral Clock Selection Register 1 (PCLKSEL1) // <o10.0..1> PCLK_QEI: Peripheral Clock Selection for the Quadrature Encoder Interface // <0=> Pclk = Cclk / 4 // <1=> Pclk = Cclk // <2=> Pclk = Cclk / 2 // <3=> Pclk = Hclk / 8 // <o10.2..3> PCLK_GPIO: Peripheral Clock Selection for GPIOs // <0=> Pclk = Cclk / 4 // <1=> Pclk = Cclk // <2=> Pclk = Cclk / 2 // <3=> Pclk = Hclk / 8 // <o10.4..5> PCLK_PCB: Peripheral Clock Selection for the Pin Connect Block // <0=> Pclk = Cclk / 4 // <1=> Pclk = Cclk // <2=> Pclk = Cclk / 2 // <3=> Pclk = Hclk / 8 // <o10.6..7> PCLK_I2C1: Peripheral Clock Selection for I2C1 // <0=> Pclk = Cclk / 4 //