ret : IN std_logic;
sdata : IN std_logic_vector(11 DOWNTO 0);
datacrco : OUT std_logic_vector(16 DOWNTO 0);
datacrci : IN std_logic_vector(16 DOWNTO 0);
rdata : OUT std_logic_vector(11 DOWNTO 0);
datafini : OUT std_logic;
ERROR0, hsend : OUT std_logic);
END crcm;
ARCHITECTURE comm OF crcm IS
CONSTANT multi_coef : std_logic_vector(5 DOWNTO 0) := "110101";
SIGNAL cnt,rcnt : std_logic_vector(3 DOWNTO 0);
SIGNAL dtemp,sdatam,rdtemp : std_logic_vector(11 DOWNTO 0);
SIGNAL rdatacrc: std_logic_vector(16 DOWNTO 0);
SIGNAL st,rt : std_logic;
BEGIN
PROCESS(clk)
VARIABLE crcvar : std_logic_vector(5 DOWNTO 0);
BEGIN
IF(ret='1') THEN st<='0';
ELSIF(clk'event AND clk = '1') THEN
IF(st = '0' AND datald = '1') THEN dtemp <= sdata;
sdatam <= sdata; cnt <= (OTHERS => '0'); hsend <= '0'; st <= '1';
ELSIF(st = '1' AND cnt < 7) THEN cnt <= cnt + 1;
IF(dtemp(11) = '1') THEN crcvar := dtemp(11 DOWNTO 6) XOR multi_coef;
dtemp <= crcvar(4 DOWNTO 0) & dtemp(5 DOWNTO 0) & '0';
ELSE dtemp <= dtemp(10 DOWNTO 0) & '0'; END IF;
ELSIF(st='1' AND cnt=7) THEN datacrco<=sdatam & dtemp(11 DOWNTO 7);
hsend <= '1'; cnt <= cnt + 1;
ELSIF(st='1' AND cnt=8) THEN hsend<= '0'; st<='0';
END IF;
END IF;
END PROCESS;
PROCESS(hrecv,clk)
VARIABLE rcrcvar : std_logic_vector(5 DOWNTO 0);
BEGIN
IF(ret='1') THEN rt<='0';
ELSIF(clk'event AND clk = '1') THEN
IF(rt = '0' AND hrecv = '1') THEN rdtemp <= datacrci(16 DOWNTO 5);
rdatacrc <= datacrci; rcnt <= (OTHERS => '0');
ERROR0 <= '0'; rt <= '1';
ELSIF(rt= '1' AND rcnt < 7) THEN datafini <= '0'; rcnt <= rcnt + 1;
rcrcvar := rdtemp(11 DOWNTO 6) XOR multi_coef;
IF(rdtemp(11) = '1') THEN
