adc.rar_9260_at9260

//----------------------------------------------------------------------------- // ATMEL Microcontroller Software Support - ROUSSET - //----------------------------------------------------------------------------- // DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR // IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF // MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE // DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, // INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT // LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, // OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF // LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING // NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, // EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. //*---------------------------------------------------------------------------- //* File Name : Cstartup_SAM9.c //* Object : Low level initializations written in C for IAR //* tools //* Creation : 12/Jun/04 //* 1.2 28/Feb/05 JPP : LIB change AT91C_WDTC_WDDIS & PLL //*---------------------------------------------------------------------------- // Include the board file description #include "project.h" // The following functions must be write in ARM mode this function called directly // by exception vector extern void AT91F_Spurious_handler(void); extern void AT91F_Default_IRQ_handler(void); extern void AT91F_Default_FIQ_handler(void); //*---------------------------------------------------------------------------- //* \fn AT91F_TestRemap //* \brief This function test if the SRAM is remapped to zero //* \return value: //* 0 : Remap done //* 1 : Remap not Done //*---------------------------------------------------------------------------- unsigned int AT91F_TestRemap() { volatile unsigned int *pSram = (unsigned int *)0; unsigned int val, data_test; val = *pSram; (val != 0xAA55AA55)?(data_test=0xAA55AA55):(data_test=0x55AA55AA); *pSram = data_test; (*pSram == data_test)?(data_test = 0):(data_test=1); *pSram = val; return data_test; } //*---------------------------------------------------------------------------*/ //* Function Name : AT91F_SetPLL //* Object : Set the PLLA to 200 and Master clock to 100 Mhz //*---------------------------------------------------------------------------*/ static void AT91F_SetPLL(void) { AT91PS_PMC pPmc = AT91C_BASE_PMC; /////////////////////////////////////////////////////////////////////////// // Init PMC Step 1. Enable Main Oscillator // Main Oscillator startup time is board specific: // Main Oscillator Startup Time worst case (18MHz) corresponds to 1,4ms // (0x08 for AT91C_CKGR_OSCOUNT field) /////////////////////////////////////////////////////////////////////////// pPmc->PMC_MOR = (( AT91C_CKGR_OSCOUNT & (0x8 <<8) | AT91C_CKGR_MOSCEN )); // Wait Main Oscillator stabilization while(!(pPmc->PMC_SR & AT91C_PMC_MOSCS)); // Switch to main ocilator AT91C_BASE_PMC->PMC_MCKR = AT91C_PMC_CSS_MAIN_CLK; /////////////////////////////////////////////////////////////////////////// // Init PMC Step 2. // Set PLL to 96MHz (96,109MHz) and UDP Clock to 48MHz // PLL Startup time depends on PLL RC filter: worst case is choosen // UDP Clock (48,058MHz) is compliant with the Universal Serial Bus // Specification (+/- 0.25% for full speed) /* -Setup the PLL A */ AT91C_BASE_CKGR->CKGR_PLLAR = (AT91C_CKGR_SRCA) | ((172 << 16) & AT91C_CKGR_MULA) | (AT91C_CKGR_PLLACOUNT) | (AT91C_CKGR_OUTA_2) | (16); while (!(pPmc->PMC_SR & AT91C_PMC_LOCKA)); // Wait until the master clock is established for the case we already // turn on the PLL /////////////////////////////////////////////////////////////////////////// // Init PMC Step 3. // Selection of Master Clock MCK equal to (Processor Clock PCK) PLL/2=48MHz /////////////////////////////////////////////////////////////////////////// AT91C_BASE_PMC->PMC_MCKR = AT91C_PMC_CSS_PLLA_CLK | AT91C_PMC_PRES_CLK | AT91C_PMC_MDIV_2;; // Wait until the master clock is established while( !(AT91C_BASE_PMC->PMC_SR & AT91C_PMC_MCKRDY) ); } //*---------------------------------------------------------------------------- //* \fn AT91F_LowLevelInit //* \brief This function performs very low level HW initialization //*---------------------------------------------------------------------------- void AT91F_LowLevelInit(void) { unsigned int i; AT91C_BASE_CCFG->CCFG_EBICSA |= 0x1003A; if (AT91F_TestRemap()) AT91F_MATRIX_Remap_ARM (AT91C_BASE_MATRIX); /////////////////////////////////////////////////////////////////////////// // PLL setting /////////////////////////////////////////////////////////////////////////// // AT91F_SetPLL(); /////////////////////////////////////////////////////////////////////////// // Disable Watchdog (write once register) /////////////////////////////////////////////////////////////////////////// AT91C_BASE_WDTC->WDTC_WDMR = AT91C_WDTC_WDDIS; /////////////////////////////////////////////////////////////////////////// // Init AIC: assign corresponding handler for each interrupt source /////////////////////////////////////////////////////////////////////////// AT91C_BASE_AIC->AIC_SVR[0] = (int) AT91F_Default_FIQ_handler ; for (i = 1; i < 31; i++) { AT91C_BASE_AIC->AIC_SVR[i] = (int) AT91F_Default_IRQ_handler ; } AT91C_BASE_AIC->AIC_SPU = (unsigned int) AT91F_Spurious_handler; }