adc.rar_at91rm9200 a_atmel

//*---------------------------------------------------------------------------- //* ATMEL Microcontroller Software Support - ROUSSET - //*---------------------------------------------------------------------------- //* The software is delivered "AS IS" without warranty or condition of any //* kind, either express, implied or statutory. This includes without //* limitation any warranty or condition with respect to merchantability or //* fitness for any particular purpose, or against the infringements of //* intellectual property rights of others. //*---------------------------------------------------------------------------- //* File Name : init.c //* Object : Low level initialisations written in C //* Creation : FB 23/10/2002 //* //*---------------------------------------------------------------------------- #include "AT91RM9200.h" #include "lib_AT91RM9200.h" ///////////////////////////////////////////////////////////////////////////////////////////////////// ///////////////////////////////////////////////////////////////////////////////////////////////////// ///////////////////////////////////////////////////////////////////////////////////////////////////// #define FALSE 0 #define TRUE 1 #define DELAY_PLL 100 #define DELAY_MAIN_FREQ 100 ///////////////////////////////////////////////////////////////////////////////////////////////////// // Configuration for a Quartz 18.432000 MHz ///////////////////////////////////////////////////////////////////////////////////////////////////// #define PLLAR 0x20263E04 //* 179,712000 MHz for PCK #define PLLBR 0x10483E0E //* 48,054857 MHz (divider by 2 for USB) #define MCKR 0x00000202 //* PCK/3 = MCK Master Clock = 59,904000MHz with PLLA selected #define SLOWCLOCK 32768 //* In Hz ///////////////////////////////////////////////////////////////////////////////////////////////////// // Frequencies Range ///////////////////////////////////////////////////////////////////////////////////////////////////// #define INPUT_FREQ_MIN 900000 #define INPUT_FREQ_MAX 32000000 #ifdef AT91RM9200 #define BASE_EBI_CS0_ADDRESS 0x10000000 //* base address to access memory on CS0 #define BASE_EBI_CS1_ADDRESS 0x20000000 //* base address to access memory on CS1 #define OUTPUT_FREQ_MIN 80000000 #define OUTPUT_FREQ_MAX 240000000 #else #ifdef AT91RM3400 #define OUTPUT_FREQ_MIN 20000000 #define OUTPUT_FREQ_MAX 100000000 #endif #endif ///////////////////////////////////////////////////////////////////////////////////////////////////// ///////////////////////////////////////////////////////////////////////////////////////////////////// ///////////////////////////////////////////////////////////////////////////////////////////////////// //*---------------------------------------------------------------------------- //* \fn AT91F_WaitForMainClockFrequency //* \brief This function performs very low level HW initialization //*---------------------------------------------------------------------------- unsigned char AT91F_WaitForMainClockFrequency() { volatile char tmp = 0; ///////////////////////////////////////////////////////////////////////////////////////////////////// // Step 2. // Checking the Main Oscillator Frequency (Optional) ///////////////////////////////////////////////////////////////////////////////////////////////////// //* Determine the main clock frequency while(!(AT91C_BASE_CKGR->CKGR_MCFR & AT91C_CKGR_MAINRDY) && (tmp++ < DELAY_MAIN_FREQ)); if (tmp >= DELAY_MAIN_FREQ) return FALSE; return TRUE; } //*---------------------------------------------------------------------------- //* \fn AT91F_CheckPLL_FrequencyRange //* \brief This function performs very low level HW initialiszation //*---------------------------------------------------------------------------- unsigned char AT91F_CheckPLL_FrequencyRange(int MainClock,int pllDivider ,int pllMultiplier) { if(pllDivider == 0) return FALSE; //* Check Input Frequency if( ((MainClock/pllDivider) < INPUT_FREQ_MIN) || ((MainClock/pllDivider) > INPUT_FREQ_MAX) ) return FALSE; //* Check Output Frequency if( ((MainClock/pllDivider*pllMultiplier) < OUTPUT_FREQ_MIN) || ((MainClock/pllDivider*pllMultiplier) > OUTPUT_FREQ_MAX) ) return FALSE; return TRUE; } //*---------------------------------------------------------------------------- //* \fn AT91F_InitClocks //* \brief This function performs very low level HW initialization //*---------------------------------------------------------------------------- unsigned char AT91F_InitClocks(int PLLAR_Register,int PLLBR_Register ,int MCKR_Register) { volatile char tmp = 0; unsigned int MainClock; unsigned int pllDivider,pllMultiplier; ///////////////////////////////////////////////////////////////////////////////////////////////////// // Optionnal ///////////////////////////////////////////////////////////////////////////////////////////////////// //* Check if Input & Output Frequencies are in the correct range MainClock = AT91F_CKGR_GetMainClock(AT91C_BASE_CKGR,SLOWCLOCK); pllDivider = (PLLAR_Register & AT91C_CKGR_DIVA); pllMultiplier = ((PLLAR_Register & AT91C_CKGR_MULA) >> 16) + 1; if(AT91F_CheckPLL_FrequencyRange(MainClock, pllDivider , pllMultiplier) == FALSE) return FALSE; pllDivider = (PLLBR_Register & AT91C_CKGR_DIVB); pllMultiplier = ((PLLBR_Register & AT91C_CKGR_MULB) >> 16) + 1; if(AT91F_CheckPLL_FrequencyRange(MainClock, pllDivider , pllMultiplier) == FALSE) return FALSE; ///////////////////////////////////////////////////////////////////////////////////////////////////// // Step 3. // Setting PLLA and Divider A ///////////////////////////////////////////////////////////////////////////////////////////////////// AT91C_BASE_CKGR->CKGR_PLLAR = PLLAR_Register; //* Wait for PLLA stabilization LOCKA bit in PMC_SR tmp = 0; while( !(AT91C_BASE_PMC->PMC_SR & AT91C_PMC_LOCKA) && (tmp++ < DELAY_PLL) ) ; ///////////////////////////////////////////////////////////////////////////////////////////////////// // Step 4. // Setting PLLB and Divider B ///////////////////////////////////////////////////////////////////////////////////////////////////// AT91C_BASE_CKGR->CKGR_PLLBR = PLLBR_Register; //* Wait for PLLB stabilization LOCKB bit in PMC_SR tmp = 0; while( !(AT91C_BASE_PMC->PMC_SR & AT91C_PMC_LOCKB) && (tmp++ < DELAY_PLL) ) ; ///////////////////////////////////////////////////////////////////////////////////////////////////// // Step 5. // Selection of Master Clock MCK (and Processor Clock PCK) ///////////////////////////////////////////////////////////////////////////////////////////////////// //* Constraints of the Master Clock selection sequence //* Write in the MCKR dirty value concerning the clock selection CSS then overwrite it in a second sequence AT91C_BASE_PMC->PMC_MCKR = AT91C_PMC_CSS_SLOW_CLK; //* Wait until the master clock is established tmp = 0; while( !(AT91C_BASE_PMC->PMC_SR & AT91C_PMC_MCKRDY) && (tmp++ < DELAY_MAIN_FREQ) ); //* Second sequence AT91C_BASE_PMC->PMC_MCKR = MCKR_Register; //* Wait until the master clock is established tmp = 0; while( !(AT91C_BASE_PMC->PMC_SR & AT91C_PMC_MCKRDY) && (tmp++ < DELAY_MAIN_FREQ) ); return TRUE; } //*---------------------------------------------------------------------------- //* \fn AT91F_InitSDRAM //* \brief This function performs very low level HW initialisation //*---------------------------------------------------------------------------- void AT91F_InitSDRAM() { int i; int *pSDRAM = (int *)BASE_EBI_CS1_ADDRESS; //* Configure PIOC as peripheral (D16/D31) AT91F_SDRC_CfgPIO(); //* Setup MEMC to support CS1=SDRAM AT91C_BASE_EBI->EBI_CSA |= AT91C_EBI_CS1A; AT91C_BASE_EBI->EBI_