DS512 September 16, 2009 www.xilinx.com 1
Product Specification
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Introduction
The Xilinx LogiCORE™ IP Block Memory Generator
core is an advanced memory constructor that generates
area and performance-optimized memories using
embedded block RAM resources in Xilinx FPGAs.
Available through the CORE Generator™ software,
users can quickly create optimized memories to
leverage the performance and features of block RAMs
in Xilinx FPGAs.
Features
• Generates Single-port RAM, Simple Dual-port
RAM, True Dual-port RAM, Single-port ROM, and
Dual-port ROM
• Performance up to 450 MHz
• Supports data widths from 1 to 1152 bits and
memory depths from 2 to 9M words (limited only
by memory resources on selected part)
• Supports configurable port aspect ratios for dual-
port configurations and read-to-write aspect ratios
in Virtex®-6, Virtex-5 and Virtex-4 FPGAs
• Optimized algorithms for minimum block RAM
resource utilization or low power utilization
• Configurable memory initialization
• Supports individual write enable per byte in
Virtex-6, Virtex-5, Virtex-4, Spartan®-6, and
Spartan-3A/XA DSP with or without parity
• Optimized VHDL and Verilog behavioral models
for fast simulation times; structural simulation
models for precise simulation of memory
behaviors
• Selectable operating mode per port: WRITE_FIRST,
READ_FIRST, or NO_CHANGE
• Supports built-in Hamming Error Correction
Capability (ECC) for Virtex-6 and Virtex-5 devices,
and associated error injection pins in Virtex-6 to
insert single and double bit errors
• Supports pipelining of DOUT bus for improved
performance in specific configurations
• Smaller primitive configurations in Spartan-6
devices with the introduction of new 9K
primitives.
• Lower data widths for Virtex-6 devices in SDP
mode.
• Choice of reset priority for output registers
between priority of SR (Set Reset) or CE (Clock
Enable) in Spartan-6 and Virtex-6 families.
• Asynchronous reset in Spartan-6 devices.
Block Memory Generator v3.3
DS512 September 16, 2009 Product Specification
LogiCORE™ IP Facts
Core Specifics
Supported
Device Family
(1)
1. See Table 1, page 2 for more details about supported de-
vices.
Virtex-6, Virtex-5, Virtex-4,
Spartan-6, Spartan-3E/XA, Spartan-3/XA,
Spartan-3A/3AN/3A DSP
Block RAM
Varied, based on core parameters
DCM
None
BUFG
None
IOBs/
Transceivers
None
PPC
None
IOB-FF/TBUFs
None
Provided with Core
Documentation
Product Specification
Migration Guide
(2)
2. The Migration Guide provides instructions for converting
designs that contain instances of either Legacy LogiCORE
IP 6.x Single or Dual Port Block Memory, or older versions
of LogiCORE Block Memory Generator to blocks of the lat-
est version of the LogiCORE Block Memory Generator.
Design File
Formats
NGC Netlist
Design Tool Requirements
Xilinx
Implementation
Tools
ISE® v11.3
Simulation
Mentor Graphics® ModelSim®: v6.4b and above
VHDL Structural
Verilog Structural
VHDL Behavioral
(3)
Verilog Behavioral
(3)
3. Behavioral models do not precisely model collision behav-
ior. See "Simulation Models," page 31 for details.
Synthesis
XST
Support
Provided by Xilinx, Inc.
