LCD.rar_LCD_LCDprojectverilog_veriloglcd_读写verilog资源-CSDN文库

共53个文件

v：8个

log：5个

htm：4个

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LCD.rar （53个子文件）

LCD实验

Source File

Clock_Gen.v 1KB

LCD_Driver.v 5KB

LCD_Top.v 559B

Project

LCD_1602

coreconsole

stimulus

hdl

hdlsynchk.tcl 114B

Clock_Gen.v 1KB

LCD_Driver.v 5KB

LCD_Top.v 559B

constraint

LCD_Top.pdc 2KB

LCD_1602.prj 6KB

LCD_1602.prj.convert.8.1.bak 6KB

component

synthesis

LCD_Top.areasrr 5KB

LCD_Top_syn.prj 798B

LCD_Top_sdc.sdc 310B

LCD_Top.sdf 181KB

stdout.log 1KB

LCD_Top.srr 46KB

LCD_Top.sap 5KB

syntmp

LCD_Top_flink.htm 352B

LCD_Top.msg 3KB

sap.log 1KB

LCD_Top_srr.htm 55KB

LCD_Top_toc.htm 2KB

LCD_Top.plg 881B

LCD_Top.srs 24KB

LCD_Top.edn 248KB

LCD_Top.tlg 8KB

LCD_Top.srm 355KB

LCD_Top.htm 332B

LCD_Top.fse 594B

LCD_Top.map 0B

LCD_Top.srd 114KB

traplog.tlg 4KB

.recordref 0B

smartgen

PLL_1M_work.ixf 1KB

PLL_1M

PLL_1M.gen 472B

PLL_1M.v 2KB

PLL_1M.log 3KB

PLL_1M.cxf 1KB

smartgen.aws 396B

designer

impl1

LCD_Top.pdb 95KB

LCD_Top.pdb.depends 0B

LCD_Top.ide_des 640B

LCD_Top.dtf

verify.log 233B

LCD_Top.adb 299KB

LCD_Top_ba.v 84KB

LCD_Top_ba.sdf 285KB

simulation

LCD_Top.tcl 172B

designer.log 10KB

phy_synthesis

viewdraw

project.lst 81B

sch

sym

wir

viewdraw.ini 2KB

simulation

modelsim.ini.sav 246B

modelsim.ini 248B

meminit.dat 3KB

<html> <body><samp><pre> <!@TC:1188895219> #Build: Synplify Pro 8.6.2H, Build 017R, Dec 7 2006 #install: D:\Libero\Synplify\Synplify_862H #OS: Windows XP 5.1 #Hostname: SHOUJINQIAO #Tue Sep 04 16:40:19 2007 <a name=compilerReport27>$ Start of Compile #Tue Sep 04 16:40:19 2007 Synplicity Verilog Compiler, version 3.7, Build 090R, built Nov 17 2006 Copyright (C) 1994-2006, Synplicity Inc. All Rights Reserved @I::"D:\Libero\Synplify\Synplify_862H\lib\proasic\fusion.v" @I::"C:\Actelprj\yan\LCD_1602\smartgen\PLL_1M\PLL_1M.v" @I::"C:\Actelprj\yan\LCD_1602\hdl\Clock_Gen.v" @I::"C:\Actelprj\yan\LCD_1602\hdl\LCD_Driver.v" @I::"C:\Actelprj\yan\LCD_1602\hdl\LCD_Top.v" Verilog syntax check successful! Compiler output is up to date. No re-compile necessary Selecting top level module LCD_Top @N:<a href="@N:CG364:@XP_HELP">CG364</a> : <a href="d:\libero\synplify\synplify_862h\lib\proasic\fusion.v:2043:7:2043:10:@N:CG364:@XP_MSG">fusion.v(2043)</a><!@TM:1188895219> | Synthesizing module VCC @N:<a href="@N:CG364:@XP_HELP">CG364</a> : <a href="d:\libero\synplify\synplify_862h\lib\proasic\fusion.v:1224:7:1224:10:@N:CG364:@XP_MSG">fusion.v(1224)</a><!@TM:1188895219> | Synthesizing module GND @N:<a href="@N:CG364:@XP_HELP">CG364</a> : <a href="d:\libero\synplify\synplify_862h\lib\proasic\fusion.v:2974:7:2974:10:@N:CG364:@XP_MSG">fusion.v(2974)</a><!@TM:1188895219> | Synthesizing module PLL @N:<a href="@N:CG364:@XP_HELP">CG364</a> : <a href="d:\libero\synplify\synplify_862h\lib\proasic\fusion.v:260:7:260:13:@N:CG364:@XP_MSG">fusion.v(260)</a><!@TM:1188895219> | Synthesizing module PLLINT @N:<a href="@N:CG364:@XP_HELP">CG364</a> : <a href="c:\actelprj\yan\lcd_1602\smartgen\pll_1m\pll_1m.v:5:7:5:13:@N:CG364:@XP_MSG">pll_1m.v(5)</a><!@TM:1188895219> | Synthesizing module PLL_1M @N:<a href="@N:CG364:@XP_HELP">CG364</a> : <a href="c:\actelprj\yan\lcd_1602\hdl\clock_gen.v:5:7:5:16:@N:CG364:@XP_MSG">clock_gen.v(5)</a><!@TM:1188895219> | Synthesizing module Clock_Gen @N:<a href="@N:CG179:@XP_HELP">CG179</a> : <a href="c:\actelprj\yan\lcd_1602\hdl\clock_gen.v:35:27:35:34:@N:CG179:@XP_MSG">clock_gen.v(35)</a><!@TM:1188895219> | Removing redundant assignment @W:<a href="@W:CS148:@XP_HELP">CS148</a> : <a href="c:\actelprj\yan\lcd_1602\hdl\clock_gen.v:15:12:15:14:@W:CS148:@XP_MSG">clock_gen.v(15)</a><!@TM:1188895219> | Undriven input OADIVRST, tying to 0 @N:<a href="@N:CG364:@XP_HELP">CG364</a> : <a href="c:\actelprj\yan\lcd_1602\hdl\lcd_driver.v:7:7:7:17:@N:CG364:@XP_MSG">lcd_driver.v(7)</a><!@TM:1188895219> | Synthesizing module LCD_Driver @W:<a href="@W:CL112:@XP_HELP">CL112</a> : <a href="c:\actelprj\yan\lcd_1602\hdl\lcd_driver.v:43:0:43:6:@W:CL112:@XP_MSG">lcd_driver.v(43)</a><!@TM:1188895219> | Feedback mux created for signal Data_Second_Buf[111:0]. Did you forget the set/reset assignment for this signal? @W:<a href="@W:CL112:@XP_HELP">CL112</a> : <a href="c:\actelprj\yan\lcd_1602\hdl\lcd_driver.v:43:0:43:6:@W:CL112:@XP_MSG">lcd_driver.v(43)</a><!@TM:1188895219> | Feedback mux created for signal Data_First_Buf[111:0]. Did you forget the set/reset assignment for this signal? @W:<a href="@W:CL189:@XP_HELP">CL189</a> : <a href="c:\actelprj\yan\lcd_1602\hdl\lcd_driver.v:43:0:43:6:@W:CL189:@XP_MSG">lcd_driver.v(43)</a><!@TM:1188895219> | Register bit Data_First_Buf[3] is always 0, optimizing ... @W:<a href="@W:CL189:@XP_HELP">CL189</a> : <a href="c:\actelprj\yan\lcd_1602\hdl\lcd_driver.v:43:0:43:6:@W:CL189:@XP_MSG">lcd_driver.v(43)</a><!@TM:1188895219> | Register bit Data_First_Buf[4] is always 0, optimizing ... @W:<a href="@W:CL189:@XP_HELP">CL189</a> : <a href="c:\actelprj\yan\lcd_1602\hdl\lcd_driver.v:43:0:43:6:@W:CL189:@XP_MSG">lcd_driver.v(43)</a><!@TM:1188895219> | Register bit Data_First_Buf[5] is always 0, optimizing ... @W:<a href="@W:CL189:@XP_HELP">CL189</a> : <a href="c:\actelprj\yan\lcd_1602\hdl\lcd_driver.v:43:0:43:6:@W:CL189:@XP_MSG">lcd_driver.v(43)</a><!@TM:1188895219> | Register bit Data_First_Buf[7] is always 0, optimizing ... @W:<a href="@W:CL189:@XP_HELP">CL189</a> : <a href="c:\actelprj\yan\lcd_1602\hdl\lcd_driver.v:43:0:43:6:@W:CL189:@XP_MSG">lcd_driver.v(43)</a><!@TM:1188895219> | Register bit Data_Second_Buf[1] is always 0, optimizing ... @W:<a href="@W:CL189:@XP_HELP">CL189</a> : <a href="c:\actelprj\yan\lcd_1602\hdl\lcd_driver.v:43:0:43:6:@W:CL189:@XP_MSG">lcd_driver.v(43)</a><!@TM:1188895219> | Register bit Data_Second_Buf[4] is always 0, optimizing ... @W:<a href="@W:CL189:@XP_HELP">CL189</a> : <a href="c:\actelprj\yan\lcd_1602\hdl\lcd_driver.v:43:0:43:6:@W:CL189:@XP_MSG">lcd_driver.v(43)</a><!@TM:1188895219> | Register bit Data_Second_Buf[7] is always 0, optimizing ... @W:<a href="@W:CL171:@XP_HELP">CL171</a> : <a href="c:\actelprj\yan\lcd_1602\hdl\lcd_driver.v:43:0:43:6:@W:CL171:@XP_MSG">lcd_driver.v(43)</a><!@TM:1188895219> | Pruning Register bit <7> of Data_First_Buf[111:0] @W:<a href="@W:CL171:@XP_HELP">CL171</a> : <a href="c:\actelprj\yan\lcd_1602\hdl\lcd_driver.v:43:0:43:6:@W:CL171:@XP_MSG">lcd_driver.v(43)</a><!@TM:1188895219> | Pruning Register bit <5> of Data_First_Buf[111:0] @W:<a href="@W:CL171:@XP_HELP">CL171</a> : <a href="c:\actelprj\yan\lcd_1602\hdl\lcd_driver.v:43:0:43:6:@W:CL171:@XP_MSG">lcd_driver.v(43)</a><!@TM:1188895219> | Pruning Register bit <4> of Data_First_Buf[111:0] @W:<a href="@W:CL171:@XP_HELP">CL171</a> : <a href="c:\actelprj\yan\lcd_1602\hdl\lcd_driver.v:43:0:43:6:@W:CL171:@XP_MSG">lcd_driver.v(43)</a><!@TM:1188895219> | Pruning Register bit <3> of Data_First_Buf[111:0] @W:<a href="@W:CL171:@XP_HELP">CL171</a> : <a href="c:\actelprj\yan\lcd_1602\hdl\lcd_driver.v:43:0:43:6:@W:CL171:@XP_MSG">lcd_driver.v(43)</a><!@TM:1188895219> | Pruning Register bit <7> of Data_Second_Buf[111:0] @W:<a href="@W:CL171:@XP_HELP">CL171</a> : <a href="c:\actelprj\yan\lcd_1602\hdl\lcd_driver.v:43:0:43:6:@W:CL171:@XP_MSG">lcd_driver.v(43)</a><!@TM:1188895219> | Pruning Register bit <4> of Data_Second_Buf[111:0] @W:<a href="@W:CL171:@XP_HELP">CL171</a> : <a href="c:\actelprj\yan\lcd_1602\hdl\lcd_driver.v:43:0:43:6:@W:CL171:@XP_MSG">lcd_driver.v(43)</a><!@TM:1188895219> | Pruning Register bit <1> of Data_Second_Buf[111:0] @N:<a href="@N:CG364:@XP_HELP">CG364</a> : <a href="c:\actelprj\yan\lcd_1602\hdl\lcd_top.v:5:7:5:14:@N:CG364:@XP_MSG">lcd_top.v(5)</a><!@TM:1188895219> | Synthesizing module LCD_Top @W:<a href="@W:CL189:@XP_HELP">CL189</a> : <a href="c:\actelprj\yan\lcd_1602\hdl\lcd_driver.v:43:0:43:6:@W:CL189:@XP_MSG">lcd_driver.v(43)</a><!@TM:1188895219> | Register bit Data_First_Buf[12] is always 0, optimizing ... @W:<a href="@W:CL189:@XP_HELP">CL189</a> : <a href="c:\actelprj\yan\lcd_1602\hdl\lcd_driver.v:43:0:43:6:@W:CL189:@XP_MSG">lcd_driver.v(43)</a><!@TM:1188895219> | Register bit Data_First_Buf[13] is always 0, optimizing ... @W:<a href="@W:CL189:@XP_HELP">CL189</a> : <a href="c:\actelprj\yan\lcd_1602\hdl\lcd_driver.v:43:0:43:6:@W:CL189:@XP_MSG">lcd_driver.v(43)</a><!@TM:1188895219> | Register bit Data_First_Buf[15] is always 0, optimizing ... @W:<a href="@W:CL189:@XP_HELP">CL189</a> : <a href="c:\actelprj\yan\lcd_1602\hdl\lcd_driver.v:43:0:43:6:@W:CL189:@XP_MSG">lcd_driver.v(43)</a><!@TM:1188895219> | Register bit Data_Second_Buf[12] is always 0, optimizing ... @W:<a href="@W:CL189:@XP_HELP">CL189</a> : <a href="c:\actelprj\yan\lcd_1602\hdl\lcd_driver.v:43:0:43:

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