library ieee ;
use ieee.std_logic_1164.all ;
use ieee.std_logic_unsigned.all ;
entity rxcver is
port (
reset : in std_logic ;
clk16x: in std_logic ;
rxd : in std_logic ;
temp_clk1xen : out std_logic;
dout : out std_logic_vector (7 downto 0) ;
temp_length: out std_logic_vector(3 downto 0);
temp_clkdiv: out std_logic_vector(3 downto 0);
temp_clk : out std_logic ;
temp_rxd1 : out std_logic;
temp_rxd2 : out std_logic;
temp_clk1x : out std_logic;
write_en: out std_logic;
temp_error : out std_logic
) ;
end rxcver ;
architecture v1 of rxcver is
signal rxd1 : std_logic ;
signal rxd2 : std_logic ;
signal we_fifo_clk:std_logic;
signal framing_error:std_logic;
signal clk1x_en ,writeen: std_logic ;
signal clkdiv : std_logic_vector (3 downto 0) ;
signal rsr : std_logic_vector (7 downto 0) ;
signal length : std_logic_vector (3 downto 0) ;
signal clk1x : std_logic ;
begin
p1:process (reset,clk16x)
begin
if reset = '0' then
rxd1 <= '1' ;
rxd2 <= '1' ;
elsif clk16x'event and clk16x = '1' then
rxd1 <= rxd ;
rxd2 <= rxd1 ;
end if ;
end process p1;
p2:process (reset,clk16x)
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