four_bit-data-selector.rar_four

Debug for fit_fastio_pin_reassign program (iteration 1): I/O delay matrix:- Comb Reg SU Pin Cout Casc Clk N/A 44 N/A 44 N/A N/A Clr N/A 54 N/A 54 N/A N/A Pre N/A 54 N/A 54 N/A N/A Ena N/A N/A 32 N/A N/A N/A Ald N/A 54 N/A 54 N/A N/A OE N/A N/A N/A 61 N/A N/A Cin N/A N/A N/A N/A N/A N/A Casc N/A N/A N/A N/A N/A N/A Pin 35 N/A 135 N/A N/A N/A A N/A N/A 25 35 N/A N/A B N/A N/A N/A N/A N/A N/A C N/A N/A N/A N/A N/A N/A D N/A N/A N/A N/A N/A N/A Global clock delay matrix:- Comb Reg SU Pin Cout Casc Clk : N/A 26 52 N/A 38 N/A Clr : N/A 27 N/A N/A 39 N/A Pre : N/A 27 N/A N/A 39 N/A Ena : N/A N/A 22 N/A N/A N/A Ald : N/A 27 N/A N/A 39 N/A OE : N/A N/A N/A N/A N/A N/A Cin : 13 N/A 17 N/A 3 15 Casc: 7 N/A 11 N/A N/A 9 Pin : N/A N/A N/A N/A N/A N/A A : 23 N/A 27 N/A 12 25 B : 23 N/A 27 N/A 12 25 C : 23 N/A 27 N/A N/A 25 D : 18 N/A 22 N/A N/A 20 I/O delay matrix:- Comb Reg SU Pin Cout Casc Clk N/A 44 N/A 44 N/A N/A Clr N/A 54 N/A 54 N/A N/A Pre N/A 54 N/A 54 N/A N/A Ena N/A N/A 32 N/A N/A N/A Ald N/A 54 N/A 54 N/A N/A OE N/A N/A N/A 61 N/A N/A Cin N/A N/A N/A N/A N/A N/A Casc N/A N/A N/A N/A N/A N/A Pin 35 N/A 135 N/A N/A N/A A N/A N/A 25 35 N/A N/A B N/A N/A N/A N/A N/A N/A C N/A N/A N/A N/A N/A N/A D N/A N/A N/A N/A N/A N/A Global clock delay matrix:- Comb Reg SU Pin Cout Casc Clk : N/A 26 52 N/A 38 N/A Clr : N/A 27 N/A N/A 39 N/A Pre : N/A 27 N/A N/A 39 N/A Ena : N/A N/A 22 N/A N/A N/A Ald : N/A 27 N/A N/A 39 N/A OE : N/A N/A N/A N/A N/A N/A Cin : 13 N/A 17 N/A 3 15 Casc: 7 N/A 11 N/A N/A 9 Pin : N/A N/A N/A N/A N/A N/A A : 23 N/A 27 N/A 12 25 B : 23 N/A 27 N/A 12 25 C : 23 N/A 27 N/A N/A 25 D : 18 N/A 22 N/A N/A 20 Threshold are: for Tsu - 10.600000ns and for Tco - 17.700000ns Global Tsu=-1(-1.000000), Tco=-1(-1.000000) Input/output cells: A0 : IN A1 : IN B0 : IN B1 : IN C0 : IN C1 : IN D0 : IN D1 : IN Oput0 : OUT Oput1 : OUT sel_0 : IN sel_1 : IN Set clique dont_touch: Cell: A0, rdfbits: 5, fast_io bit: 0, periphery: 0,0 Cell: A1, rdfbits: 5, fast_io bit: 0, periphery: 0,0 Cell: B0, rdfbits: 5, fast_io bit: 0, periphery: 0,0 Cell: B1, rdfbits: 5, fast_io bit: 0, periphery: 0,0 Cell: C0, rdfbits: 5, fast_io bit: 0, periphery: 0,0 Cell: C1, rdfbits: 5, fast_io bit: 0, periphery: 0,0 Cell: D0, rdfbits: 5, fast_io bit: 0, periphery: 0,0 Cell: D1, rdfbits: 5, fast_io bit: 0, periphery: 0,0 Cell: Oput0, rdfbits: 3, fast_io bit: 0, periphery: 0,0 Cell: Oput1, rdfbits: 3, fast_io bit: 0, periphery: 0,0 Cell: sel_0, rdfbits: 5, fast_io bit: 0, periphery: 0,0 Cell: sel_1, rdfbits: 5, fast_io bit: 0, periphery: 0,0 Cell: ~33~1, rdfbits: 1050, fast_io bit: 0, periphery: 0,0 Cell: ~33~2, rdfbits: 1050, fast_io bit: 0, periphery: 0,0 Cell: :33, rdfbits: 50, fast_io bit: 0, periphery: 0,0 Cell: ~34~1, rdfbits: 1050, fast_io bit: 0, periphery: 0,0 Cell: ~34~2, rdfbits: 1050, fast_io bit: 0, periphery: 0,0 Cell: :34, rdfbits: 50, fast_io bit: 0, periphery: 0,0 Virtual pin individual set-up and clock-to-output times: For pin A0 delays are: tsu=-1, tco=-1; For pin A1 delays are: tsu=-1, tco=-1; For pin B0 delays are: tsu=-1, tco=-1; For pin B1 delays are: tsu=-1, tco=-1; For pin C0 delays are: tsu=-1, tco=-1; For pin C1 delays are: tsu=-1, tco=-1; For pin D0 delays are: tsu=-1, tco=-1; For pin D1 delays are: tsu=-1, tco=-1; For pin Oput0 delays are: tsu=-1, tco=-1; For pin Oput1 delays are: tsu=-1, tco=-1; For pin sel_0 delays are: tsu=-1, tco=-1; For pin sel_1 delays are: tsu=-1, tco=-1; Cells driven by pins ~34~1 is driven by A0 ~33~1 is driven by A1 ~34~1 is driven by B0 ~33~1 is driven by B1 ~34~2 is driven by C0 ~33~2 is driven by C1 ~34~2 is driven by D0 ~33~2 is driven by D1 ~33~1 is driven by sel_0 ~33~2 is driven by sel_0 ~34~1 is driven by sel_0 ~34~2 is driven by sel_0 ~33~1 is driven by sel_1 ~33~2 is driven by sel_1 ~34~1 is driven by sel_1 ~34~2 is driven by sel_1 Cells driving pins :34 drives Oput0 :33 drives Oput1 FAST I/O assignement after cleaning up: A0: fast_io=0 A1: fast_io=0 B0: fast_io=0 B1: fast_io=0 C0: fast_io=0 C1: fast_io=0 D0: fast_io=0 D1: fast_io=0 Oput0: fast_io=0 Oput1: fast_io=0 sel_0: fast_io=0 sel_1: fast_io=0 Layer-by-layer logic: fast_io=0 Layer 0 A0, RDF bits: 5, lab#=0 A1, RDF bits: 5, lab#=0 B0, RDF bits: 5, lab#=0 B1, RDF bits: 5, lab#=0 C0, RDF bits: 5, lab#=0 C1, RDF bits: 5, lab#=0 D0, RDF bits: 5, lab#=0 D1, RDF bits: 5, lab#=0 Oput0, RDF bits: 3, lab#=0 Oput1, RDF bits: 3, lab#=0 sel_0, RDF bits: 5, lab#=0 sel_1, RDF bits: 5, lab#=0 Layer 1 ~33~1, RDF bits: 1050, lab#=0 ~33~2, RDF bits: 1050, lab#=0 :33, RDF bits: 50, lab#=0 ~34~1, RDF bits: 1050, lab#=0 ~34~2, RDF bits: 1050, lab#=0 :34, RDF bits: 50, lab#=0 Physical pins available: row: 0, col: -1 RDF: 800003c7 row: 0, col: -1 RDF: 800003c7 row: 0, col: -1 RDF: 800003c7 row: 0, col: -1 RDF: 800003c7 row: 1, col: -1 RDF: 800003c7 row: 1, col: -1 RDF: 800003c7 row: 1, col: -1 RDF: 800003c7 row: 1, col: -1 RDF: 800003c7 row: 1, col: -1 RDF: 800003c7 row: 2, col: -1 RDF: 800003c7 row: 2, col: -1 RDF: 800003c7 row: 2, col: -1 RDF: 800003c7 row: 2, col: -1 RDF: 800003c7 row: -1, col: 5 RDF: 800003c7 row: -1, col: 6 RDF: 800003c7 row: -1, col: 8 RDF: 800003c7 row: -1, col: 9 RDF: 800003c7 row: -1, col: 10 RDF: 800003c7 row: -1, col: -1 RDF: 4600080d row: -1, col: -1 RDF: d row: -1, col: -1 RDF: 4600080d row: -1, col: 13 RDF: 800003c7 row: -1, col: 14 RDF: 800003c7 row: -1, col: 15 RDF: 800003c7 row: -1, col: 16 RDF: 800003c7 row: -1, col: 17 RDF: 800003c7 row: -1, col: 18 RDF: 800003c7 row: -1, col: 19 RDF: 800003c7 row: -1, col: 20 RDF: 800003c7 row: 2, col: -1 RDF: 800003c7 row: 2, col: -1 RDF: 800003c7 row: 2, col: -1 RDF: 800003c7 row: 2, col: -1 RDF: 800003c7 row: 2, col: -1 RDF: 800003c7 row: 1, col: -1 RDF: 800003c7 row: 1, col: -1 RDF: 800003c7 row: 1, col: -1 RDF: 800003c7 row: 1, col: -1 RDF: 800003c7 58. 69 (INIT_DONE) row: 0, col: -1 RDF: 800003c7 59. 70 (RDYnBUSY) row: 0, col: -1 RDF: 800003c7 row: 0, col: -1 RDF: 800003c7 row: 0, col: -1 RDF: 800003c7 62. 73 (CLKUSR) row: 0, col: -1 RDF: 800003c7 67. 78 (nCS) row: -1, col: 23 RDF: 800003c7 68. 79 (CS) row: -1, col: 23 RDF: 800003c7 69. 80 (nWS) row: -1, col: 22 RDF: 800003c7 70. 81 (nRS) row: -1, col: 21 RDF: 800003c7 72. 83 (DEV_OE) row: -1, col: 12 RDF: 800003c7 row: -1, col: -1 RDF: 4600080d row: -1, col: -1 RDF: d row: -1, col: -1 RDF: 4600080d 76. 3 (DEV_CLRn) row: -1, col: 11 RDF: 800003c7 78. 5 (DATA7) row: -1, col: 4 RDF: 800003c7 79. 6 (DATA6) row: -1, col: 3 RDF: 800003c7 80. 7 (DATA5) row: -1, col: 2 RDF: 800003c7 81. 8 (DATA4) row: -1, col: 2 RDF: 800003c7 82. 9 (DATA3) row: -1, col: 1 RDF: 800003c7 83. 10 (DATA2) row: -1, col: 0 RDF: 800003c7 84. 11 (DATA1) row: -1, col: 0 RDF: 800003c7 Sorted pins: Pin sel_0: Link strength=640, fast_io=0, group No.=0 Pin sel_1: Link strength=640, fast_io=0, group No.=0 Pin A0: Link strength=328, fast_io=0, group No.=0 Pin A1: Link strength=328, fast_io=0, group No.=0 Pin B0: Link strength=328, fast_io=0, group No.=0 Pin B1: Link strength=328, fast_io=0, group No.=0 Pin C0: Link strength=328, fast_io=0, group No.=0 Pin C1: Link strength=328, fast_io=0, group No.=0 Pin D0: Link strength=328, fast_io=0, group No.=0 Pin D1: Link strength=328, fast_io=0, group No.=0 Pin Oput0: Link strength=228, fast_io=0, group No.=0 Pin Oput1: Link strength=228, fast_io=0, group No.=0 Output pin initial assignments: Initially output pin Oput0 is assigned to pin 16(index:5) Initially output pin Oput1 is assigned to pin 17(index:6) All the rest pin assignments: Initially pin sel_0 is assigned to pin 18(index:7, cost:6401) Initially pin sel_1 is assigned to pin 19(index