four_bit-full-adder.rar_2421_8421_8421码和2421码_full

Debug for fit_fastio_pin_reassign program (iteration 1): I/O delay matrix:- Comb Reg SU Pin Cout Casc Clk N/A 44 N/A 44 N/A N/A Clr N/A 54 N/A 54 N/A N/A Pre N/A 54 N/A 54 N/A N/A Ena N/A N/A 32 N/A N/A N/A Ald N/A 54 N/A 54 N/A N/A OE N/A N/A N/A 61 N/A N/A Cin N/A N/A N/A N/A N/A N/A Casc N/A N/A N/A N/A N/A N/A Pin 35 N/A 135 N/A N/A N/A A N/A N/A 25 35 N/A N/A B N/A N/A N/A N/A N/A N/A C N/A N/A N/A N/A N/A N/A D N/A N/A N/A N/A N/A N/A Global clock delay matrix:- Comb Reg SU Pin Cout Casc Clk : N/A 26 52 N/A 38 N/A Clr : N/A 27 N/A N/A 39 N/A Pre : N/A 27 N/A N/A 39 N/A Ena : N/A N/A 22 N/A N/A N/A Ald : N/A 27 N/A N/A 39 N/A OE : N/A N/A N/A N/A N/A N/A Cin : 13 N/A 17 N/A 3 15 Casc: 7 N/A 11 N/A N/A 9 Pin : N/A N/A N/A N/A N/A N/A A : 23 N/A 27 N/A 12 25 B : 23 N/A 27 N/A 12 25 C : 23 N/A 27 N/A N/A 25 D : 18 N/A 22 N/A N/A 20 I/O delay matrix:- Comb Reg SU Pin Cout Casc Clk N/A 44 N/A 44 N/A N/A Clr N/A 54 N/A 54 N/A N/A Pre N/A 54 N/A 54 N/A N/A Ena N/A N/A 32 N/A N/A N/A Ald N/A 54 N/A 54 N/A N/A OE N/A N/A N/A 61 N/A N/A Cin N/A N/A N/A N/A N/A N/A Casc N/A N/A N/A N/A N/A N/A Pin 35 N/A 135 N/A N/A N/A A N/A N/A 25 35 N/A N/A B N/A N/A N/A N/A N/A N/A C N/A N/A N/A N/A N/A N/A D N/A N/A N/A N/A N/A N/A Global clock delay matrix:- Comb Reg SU Pin Cout Casc Clk : N/A 26 52 N/A 38 N/A Clr : N/A 27 N/A N/A 39 N/A Pre : N/A 27 N/A N/A 39 N/A Ena : N/A N/A 22 N/A N/A N/A Ald : N/A 27 N/A N/A 39 N/A OE : N/A N/A N/A N/A N/A N/A Cin : 13 N/A 17 N/A 3 15 Casc: 7 N/A 11 N/A N/A 9 Pin : N/A N/A N/A N/A N/A N/A A : 23 N/A 27 N/A 12 25 B : 23 N/A 27 N/A 12 25 C : 23 N/A 27 N/A N/A 25 D : 18 N/A 22 N/A N/A 20 Threshold are: for Tsu - 10.600000ns and for Tco - 17.700000ns Global Tsu=-1(-1.000000), Tco=-1(-1.000000) Input/output cells: A0 : IN A1 : IN A2 : IN A3 : IN B0 : IN B1 : IN B2 : IN B3 : IN Co : OUT S0 : OUT S1 : OUT S2 : OUT S3 : OUT Set clique dont_touch: Cell: A0, rdfbits: 5, fast_io bit: 0, periphery: 0,0 Cell: A1, rdfbits: 5, fast_io bit: 0, periphery: 0,0 Cell: A2, rdfbits: 5, fast_io bit: 0, periphery: 0,0 Cell: A3, rdfbits: 5, fast_io bit: 0, periphery: 0,0 Cell: B0, rdfbits: 5, fast_io bit: 0, periphery: 0,0 Cell: B1, rdfbits: 5, fast_io bit: 0, periphery: 0,0 Cell: B2, rdfbits: 5, fast_io bit: 0, periphery: 0,0 Cell: B3, rdfbits: 5, fast_io bit: 0, periphery: 0,0 Cell: Co, rdfbits: 3, fast_io bit: 0, periphery: 0,0 Cell: |full_adder4:u3|full_adder:u1|:9, rdfbits: 50, fast_io bit: 0, periphery: 0,0 Cell: |full_adder4:u3|full_adder:u1|:11, rdfbits: 50, fast_io bit: 0, periphery: 0,0 Cell: |full_adder4:u3|full_adder:u1|:12, rdfbits: 50, fast_io bit: 0, periphery: 0,0 Cell: |full_adder4:u3|full_adder:u1|:13, rdfbits: 50, fast_io bit: 0, periphery: 0,0 Cell: |full_adder4:u3|full_adder:u2|:9, rdfbits: 50, fast_io bit: 0, periphery: 0,0 Cell: |full_adder4:u3|full_adder:u2|~13~1, rdfbits: 201050, fast_io bit: 0, periphery: 0,0 Cell: |full_adder4:u3|full_adder:u2|:13, rdfbits: 50, fast_io bit: 0, periphery: 0,0 Cell: |modify:u4|:113, rdfbits: 200050, fast_io bit: 0, periphery: 0,0 Cell: |modify:u4|:350, rdfbits: 50, fast_io bit: 0, periphery: 0,0 Cell: |modify:u4|:406, rdfbits: 50, fast_io bit: 0, periphery: 0,0 Cell: |modify:u4|:420, rdfbits: 50, fast_io bit: 0, periphery: 0,0 Cell: |modify:u4|:442, rdfbits: 50, fast_io bit: 0, periphery: 0,0 Cell: |modify:u4|~465~1, rdfbits: 1050, fast_io bit: 0, periphery: 0,0 Cell: |modify:u4|:466, rdfbits: 50, fast_io bit: 0, periphery: 0,0 Cell: S0, rdfbits: 3, fast_io bit: 0, periphery: 0,0 Cell: S1, rdfbits: 3, fast_io bit: 0, periphery: 0,0 Cell: S2, rdfbits: 3, fast_io bit: 0, periphery: 0,0 Cell: S3, rdfbits: 3, fast_io bit: 0, periphery: 0,0 Cell: |TtoE:u5|~85~1, rdfbits: 1050, fast_io bit: 0, periphery: 0,0 Cell: |TtoE:u5|~85~2, rdfbits: 1050, fast_io bit: 0, periphery: 0,0 Cell: |TtoE:u5|:85, rdfbits: 50, fast_io bit: 0, periphery: 0,0 Cell: |TtoE:u5|:91, rdfbits: 50, fast_io bit: 0, periphery: 0,0 Cell: |TtoE:u5|:95, rdfbits: 50, fast_io bit: 0, periphery: 0,0 Virtual pin individual set-up and clock-to-output times: For pin A0 delays are: tsu=-1, tco=-1; For pin A1 delays are: tsu=-1, tco=-1; For pin A2 delays are: tsu=-1, tco=-1; For pin A3 delays are: tsu=-1, tco=-1; For pin B0 delays are: tsu=-1, tco=-1; For pin B1 delays are: tsu=-1, tco=-1; For pin B2 delays are: tsu=-1, tco=-1; For pin B3 delays are: tsu=-1, tco=-1; For pin Co delays are: tsu=-1, tco=-1; For pin S0 delays are: tsu=-1, tco=-1; For pin S1 delays are: tsu=-1, tco=-1; For pin S2 delays are: tsu=-1, tco=-1; For pin S3 delays are: tsu=-1, tco=-1; Cells driven by pins |full_adder4:u3|full_adder:u1|:11 is driven by A0 |full_adder4:u3|full_adder:u1|:13 is driven by A0 |TtoE:u5|:95 is driven by A0 |full_adder4:u3|full_adder:u1|:9 is driven by A1 |full_adder4:u3|full_adder:u1|:12 is driven by A1 |full_adder4:u3|full_adder:u2|:9 is driven by A2 |full_adder4:u3|full_adder:u2|~13~1 is driven by A2 |full_adder4:u3|full_adder:u1|:9 is driven by A3 |full_adder4:u3|full_adder:u1|:12 is driven by A3 |full_adder4:u3|full_adder:u2|:9 is driven by A3 |full_adder4:u3|full_adder:u2|~13~1 is driven by A3 |modify:u4|:113 is driven by A3 |modify:u4|:420 is driven by A3 |modify:u4|:442 is driven by A3 |modify:u4|~465~1 is driven by A3 |modify:u4|:466 is driven by A3 |TtoE:u5|~85~1 is driven by A3 |full_adder4:u3|full_adder:u1|:11 is driven by B0 |full_adder4:u3|full_adder:u1|:13 is driven by B0 |TtoE:u5|:95 is driven by B0 |full_adder4:u3|full_adder:u1|:9 is driven by B1 |full_adder4:u3|full_adder:u1|:12 is driven by B1 |full_adder4:u3|full_adder:u2|:9 is driven by B2 |full_adder4:u3|full_adder:u2|~13~1 is driven by B2 |full_adder4:u3|full_adder:u1|:9 is driven by B3 |full_adder4:u3|full_adder:u1|:12 is driven by B3 |full_adder4:u3|full_adder:u2|:9 is driven by B3 |full_adder4:u3|full_adder:u2|~13~1 is driven by B3 |modify:u4|:113 is driven by B3 |modify:u4|:420 is driven by B3 |modify:u4|:442 is driven by B3 |modify:u4|~465~1 is driven by B3 |modify:u4|:466 is driven by B3 |TtoE:u5|~85~1 is driven by B3 Cells driving pins |modify:u4|:466 drives Co |TtoE:u5|:95 drives S0 |TtoE:u5|:91 drives S1 |TtoE:u5|:85 drives S2 |modify:u4|:420 drives S3 FAST I/O assignement after cleaning up: A0: fast_io=0 A1: fast_io=0 A2: fast_io=0 A3: fast_io=0 B0: fast_io=0 B1: fast_io=0 B2: fast_io=0 B3: fast_io=0 Co: fast_io=0 S0: fast_io=0 S1: fast_io=0 S2: fast_io=0 S3: fast_io=0 Layer-by-layer logic: fast_io=0 Layer 0 A0, RDF bits: 5, lab#=0 A1, RDF bits: 5, lab#=0 A2, RDF bits: 5, lab#=0 A3, RDF bits: 5, lab#=0 B0, RDF bits: 5, lab#=0 B1, RDF bits: 5, lab#=0 B2, RDF bits: 5, lab#=0 B3, RDF bits: 5, lab#=0 Co, RDF bits: 3, lab#=0 S0, RDF bits: 3, lab#=0 S1, RDF bits: 3, lab#=0 S2, RDF bits: 3, lab#=0 S3, RDF bits: 3, lab#=0 Layer 1 |full_adder4:u3|full_adder:u1|:9, RDF bits: 50, lab#=0 |full_adder4:u3|full_adder:u1|:11, RDF bits: 50, lab#=0 |full_adder4:u3|full_adder:u1|:12, RDF bits: 50, lab#=0 |full_adder4:u3|full_adder:u1|:13, RDF bits: 50, lab#=0 |full_adder4:u3|full_adder:u2|:9, RDF bits: 50, lab#=0 |full_adder4:u3|full_adder:u2|~13~1, RDF bits: 201050, lab#=0 |modify:u4|:113, RDF bits: 200050, lab#=0 |modify:u4|:420, RDF bits: 50, lab#=0 |modify:u4|:442, RDF bits: 50, lab#=0 |modify:u4|~465~1, RDF bits: 1050, lab#=0 |modify:u4|:466, RDF bits: 50, lab#=0 |TtoE:u5|~85~1, RDF bits: 1050, lab#=0 |TtoE:u5|:85, RDF bits: 50, lab#=0 |TtoE:u5|:91, RDF bits: 50, lab#=0 |TtoE:u5|:95, RDF bits: 50, lab#=0 Physical pins available: row: 0, col: -1 RDF: 800003c7 row: 0, col: -1 RDF: 800003c7 row: 0, col: -1 RDF: 800003c7 row: 0, col: -1 RDF: 800003c7 row: 1,