8-3coder.rar_if _priority encoder_向上相与

library; use ieee.std_logic_1164.all; entity coder is port (din: in std_logic_vector(0 to 7); output:out std_logic_vector(0 to 2) ); end coder; architecture behav of coder is signal sint:std_logic_vector(4 downto 0); begin process (din) begin if (din(7)='0') then output <="000"; elsif (din(6)='0') then output <="100"; elsif (din(5)='0') then output <="010"; elsif (din(4)='0') then output <="110"; elsif (din(3)='0') then output <="001"; elsif (din(2)='0') then output <="101"; elsif (din(1)='0') then output <="011"; else output <="111"; end if; end process; end behav; 一个时分秒计数器程序 second:process (clks) is --秒 begin if reset='1' then Q1<="0000";Q0<="0000"; elsif clks'event and clks='1' then if Q0 = "1001" then Q0<="0000"; if Q1 = "0101" then Q1<="0000"; else Q1<=Q1+1; end if; else Q0<=Q0+'1'; end if; end if; end process; enmin<='1' when Q1="0000" and Q0="0000"; minute:process (enmin) is --分 begin if reset='1' then Q3<="0000";Q2<="0000"; elsif setmin='1' then Q3<=a1;Q2<=a0; elsif enmin'event and enmin='1' then if Q2 = "1001" then Q2<="0000"; if Q3 = "0101" then Q3<="0000"; else Q3<=Q3+1; end if; else Q2<=Q2+'1'; end if; end if; end process; enhour<='1' when Q3="0000" and Q2="0000"; alert<='1' when Q3="0000" and Q2="0000" and Q1="0000" and Q0="0000"; --整点报时 hour:process (enhour) is --时 begin if reset='1' then Q5<="0000";Q4<="0000"; elsif sethour='1' then Q5<=a1;Q4<=a0; elsif enhour'event and enhour='1' then if Q5="0010" and Q4="0011" then Q5<="0000";Q4<="0000"; else if Q4="1001" then Q4<="0000";Q5<=Q5+'1'; else Q4<=Q4+'1'; end if; end if; end if; end process; 一个5进制计数器设计程序 library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; entity cnt5 is port(clk,rst:in std_logic; SEL:in std_logic_vector(1 downto 0); data1_out,data2_out,data3_out:out std_logic_vector(6 downto 0)); end cnt5; architecture arch of cnt5 is signal count:integer range 0 to 9; signal state:std_logic_vector(1 downto 0); begin process(clk,rst) begin if rst='1' then state<="00";data1_out<="1111110";data2_out<="1111110";data3_out<="1111110";count<=0; elsif clk'event and clk='1' then case state is when "00" => data1_out<="1111110";data2_out<="1111110"; if count=4 then count<=0; else count<=count+1;end if; case SEL is when "01" => state<="01";count<=0; when "10" => state<="10";count<=1; when "11" => state<="11";count<=5; when others => null; end case; when "01" => data1_out<="1111110";data2_out<="0110000"; if count=8 then count<=0; else count<=count+2;end if; case SEL is when "00" => state<="00";count<=0; when "10" => state<="10";count<=1; when "11" => state<="11";count<=5; when others => null; end case; when "10" => data1_out<="0110000";data2_out<="1111110"; if count=9 then count<=1; else count<=count+2;end if; case SEL is when "00" => state<="00";count<=0; when "01" => state<="01";count<=0; when "11" => state<="11";count<=5; when others => null; end case; when "11" => data1_out<="0110000";data2_out<="0110000"; if count=1 then count<=5; else count<=count-1;end if; case SEL is when "00" => state<="00";count<=0; when "01" => state<="01";count<=0; when "10" => state<="10";count<=1; when others => null; end case; when others => state <= "00"; end case; case count is when 0 => data3_out<="1111110"; when 1 => data3_out<="0110000"; when 2 => data3_out<="1101101"; when 3 => data3_out<="1111001"; when 4 => data3_out<="0110011"; when 5 => data3_out<="1011011"; when 6 => data3_out<="1011111"; when 7 => data3_out<="1110000"; when 8 => data3_out<="1111111"; when 9 => data3_out<="1111011"; when others => data3_out<="0000000"; end case; end if; end process; end arch;