i2c.zip_arc

/******************************************************************************* * * i2c.h * * Device driver for I2C * * Copyright (c) 2007 Chips&Media, Inc. All Rights Reserved. * ******************************************************************************/ #ifndef __I2C_H__ #define __I2C_H__ /*------------------------------------------------------------------------------ * device base register * *----------------------------------------------------------------------------*/ #define I2C_BASE 0x200e4000 /*------------------------------------------------------------------------------ * I2C OTP device registers * *----------------------------------------------------------------------------*/ #define I2C_OTP_PORT_OFFSET 0x1000 #define I2C_OTP_BASE(port) (I2C_BASE + I2C_OTP_PORT_OFFSET * port) #define I2C_OPT_FREQ(port) (I2C_OTP_BASE(port) + 0x0000) #define I2C_OPT_SLAVE_ADDR(port) (I2C_OTP_BASE(port) + 0x0004) #define I2C_OPT_SUB_ADDR(port) (I2C_OTP_BASE(port) + 0x0008) #define I2C_OPT_WDATA(port) (I2C_OTP_BASE(port) + 0x000c) #define I2C_OPT_CMD_STS(port) (I2C_OTP_BASE(port) + 0x0010) #define I2C_OPT_RDATA(port) (I2C_OTP_BASE(port) + 0x0014) #define I2C_OPT_EXT_TIME_OUT(port) (I2C_OTP_BASE(port) + 0x0018) #define I2C_OPT_CMD_START 0x1 #define I2C_OPT_CMD_READ 0x2 #define I2C_OPT_CMD_WRITE 0x0 #define I2C_OPT_CMD_SUB_WIDTH(width) ((width & 0x7) << 4) #define I2C_OPT_CMD_DATA_WIDTH(width) ((width & 0x7) << 7) #define I2C_OPT_CMD_WITHOUT_STOP 0x400 #define I2C_OPT_CMD_WITH_STOP 0x0 #define I2C_OPT_CMD_INTERRUPT_EN 0x10000 #define I2C_OPT_STS_IS_FAILED 0x00004 #define I2C_OPT_STS_IS_DONE 0x00008 #define I2C_OPT_STS_FAIL_BYTE_MASK 0x01800 #define I2C_OPT_STS_FAIL_STS_MASK 0x06000 #define I2C_OPT_STS_INTERRUPT_STS 0x08000 #define I2C_OPT_STS_FAIL_BYTE_OFFSET 11 #define I2C_OPT_STS_FAIL_STS_OFFSET 13 /*------------------------------------------------------------------------------ * I2C SMART device register * *----------------------------------------------------------------------------*/ #define I2C_SMART_BASE (I2C_BASE + I2C_OTP_PORT_OFFSET * 2) #define I2C_SMART_FREQ (I2C_SMART_BASE + 0x0000) #define I2C_SMART_SLAVE_ID (I2C_SMART_BASE + 0x0004) #define I2C_SMART_SUB_ADDR_L (I2C_SMART_BASE + 0x0008) #define I2C_SMART_SUB_ADDR_H (I2C_SMART_BASE + 0x000C) #define I2C_SMART_SUB_ADDR_SIZE (I2C_SMART_BASE + 0x0010) #define I2C_SMART_DATA_SIZE (I2C_SMART_BASE + 0x0014) #define I2C_SMART_FAIL_STATUS (I2C_SMART_BASE + 0x0018) #define I2C_SMART_FAIL_POINT (I2C_SMART_BASE + 0x001C) #define I2C_SMART_IRQ_DURATION (I2C_SMART_BASE + 0x0020) #define I2C_SMART_DATA_ADDR (I2C_SMART_BASE + 0x0024) #define I2C_SMART_CMD_STATUS (I2C_SMART_BASE + 0x0028) #define I2C_SMART_INT_SOURCE (I2C_SMART_BASE + 0x002C) #define I2C_SMART_INT_ENABLE (I2C_SMART_BASE + 0x0030) #define I2C_SMART_PORT_SELECT (I2C_SMART_BASE + 0x0034) #define I2C_SMART_PORT_ENDIAN (I2C_SMART_BASE + 0x0038) /* ID register */ #define I2C_SMART_SLAVE_ID_OFFSET 1 /* CMD/STATUS register */ #define I2C_SMART_CMD_START 0x1 #define I2C_SMART_CMD_READ 0x2 #define I2C_SMART_CMD_WRITE 0x0 #define I2C_SMART_CMD_WITHOUT_STOP 0x4 #define I2C_SMART_CMD_WITH_STOP 0x0 #define I2C_SMART_STATUS_DONE 0x8 #define I2C_SMART_STATUS_DOING 0x0 /* Interrupt register */ #define I2C_SMART_INT_SUCCESS 0x1 #define I2C_SMART_INT_FAIL 0x2 #define I2C_MAIN_CLOCK 27000000 /* 27 MHz */ #endif /* __HAL_I2C_H__ */