VHDL_reg.rar_VHDL reg_regvhdl_reg在vhdl_寄存器

VHDL编程基础－通用寄存器 做了一个简单的通用寄存器，能实现并行寄存、左移、右移等。通过mod端口控制该寄存器的工作模式，作为一般寄存器，其数据位宽实现了参数化。 仿真波形如下图所示： 源代码如下： LIBRARY ieee; USE ieee.std_logic_1164.all; ENTITY general_reg IS GENERIC( n: Positive:= 8 ); PORT ( clock : IN STD_LOGIC; serinl, serinr : IN STD_LOGIC; mode : IN STD_LOGIC_VECTOR(1 DOWNTO 0); datain : IN STD_LOGIC_VECTOR((n-1) DOWNTO 0); dataout : out STD_LOGIC_VECTOR((n-1) DOWNTO 0) ); END ENTITY general_reg; ARCHITECTURE rtl OF general_reg IS SIGNAL int_reg : STD_LOGIC_VECTOR((n-1) DOWNTO 0); BEGIN main_proc : PROCESS BEGIN WAIT UNTIL rising_edge(clock); CASE mode IS -- ?′?? WHEN "00" => int_reg <= (OTHERS => '0'); -- 2￠DD??′? WHEN "01" => int_reg <= datain; -- ×óò? WHEN "10" => int_reg <= int_reg((n-2) DOWNTO 0) & serinl; -- óòò? WHEN "11" => int_reg <= serinr & int_reg((n-1) DOWNTO 1); WHEN OTHERS => NULL; END CASE; END PROCESS; dataout <= int_reg; END rtl;