################################################################################
# Vivado (TM) v2015.4 (64-bit)
#
# README.txt: Please read the sections below to understand the steps required
# to simulate the design for a simulator, the directory structure
# and the generated exported files.
#
################################################################################
1. Simulate Design
To simulate design, cd to the simulator directory and execute the script.
For example:-
% cd questa
% ./top.sh
The export simulation flow requires the Xilinx pre-compiled simulation library
components for the target simulator. These components are referred using the
'-lib_map_path' switch. If this switch is specified, then the export simulation
will automatically set this library path in the generated script and update,
copy the simulator setup file(s) in the exported directory.
If '-lib_map_path' is not specified, then the pre-compiled simulation library
information will not be included in the exported scripts and that may cause
simulation errors when running this script. Alternatively, you can provide the
library information using this switch while executing the generated script.
For example:-
% ./top.sh -lib_map_path /design/questa/clibs
Please refer to the generated script header 'Prerequisite' section for more details.
2. Directory Structure
By default, if the -directory switch is not specified, export_simulation will
create the following directory structure:-
<current_working_directory>/export_sim/<simulator>
For example, if the current working directory is /tmp/test, export_simulation
will create the following directory path:-
/tmp/test/export_sim/questa
If -directory switch is specified, export_simulation will create a simulator
sub-directory under the specified directory path.
For example, 'export_simulation -directory /tmp/test/my_test_area/func_sim'
command will create the following directory:-
/tmp/test/my_test_area/func_sim/questa
By default, if -simulator is not specified, export_simulation will create a
simulator sub-directory for each simulator and export the files for each simulator
in this sub-directory respectively.
IMPORTANT: Please note that the simulation library path must be specified manually
in the generated script for the respective simulator. Please refer to the generated
script header 'Prerequisite' section for more details.
3. Exported script and files
Export simulation will create the driver shell script, setup files and copy the
design sources in the output directory path.
By default, when the -script_name switch is not specified, export_simulation will
create the following script name:-
<simulation_top>.sh (Unix)
When exporting the files for an IP using the -of_objects switch, export_simulation
will create the following script name:-
<ip-name>.sh (Unix)
Export simulation will create the setup files for the target simulator specified
with the -simulator switch.
For example, if the target simulator is "ies", export_simulation will create the
'cds.lib', 'hdl.var' and design library diectories and mappings in the 'cds.lib'
file.
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ethernet_test.rar_Ethernet_fpga ethernet_千兆以太网_千兆网_千兆网 fpga (180个子文件)
runme.bat 229B
runme.bat 229B
runme.bat 229B
ram.dcp 41KB
ram.dcp 41KB
compile.do 397B
compile.do 389B
simulate.do 263B
simulate.do 183B
simulate.do 158B
elaborate.do 135B
wave.do 12B
wave.do 12B
simulate.do 11B
filelist_irun.f 229B
filelist.f 131B
filelist.f 131B
filelist.f 131B
filelist.f 131B
filelist.f 131B
usage_statistics_ext_labtool.html 6KB
.xsim_webtallk.info 59B
vivado.jou 903B
vivado_3984.backup.jou 847B
vivado_4388.backup.jou 847B
vivado.jou 823B
vivado_17896.backup.jou 796B
vivado_19312.backup.jou 796B
vivado_18872.backup.jou 796B
vivado_17924.backup.jou 796B
vivado_18888.backup.jou 796B
vivado_18180.backup.jou 792B
vivado.jou 763B
ISEWrap.js 7KB
ISEWrap.js 7KB
ISEWrap.js 7KB
rundef.js 2KB
rundef.js 2KB
rundef.js 1KB
hw_ila_1.layout 241KB
runme.log 122KB
runme.log 4KB
vivado.log 2KB
vivado_4388.backup.log 1KB
vivado_3984.backup.log 1KB
vivado_18180.backup.log 1KB
summary.log 984B
summary.log 984B
summary.log 984B
summary.log 984B
summary.log 984B
summary.log 984B
summary.log 984B
labtool_webtalk.log 402B
ethernet_test.lpr 343B
.lpr 290B
vivado.pb 166KB
place_design.pb 23KB
route_design.pb 13KB
opt_design.pb 7KB
vivado.pb 7KB
write_bitstream.pb 4KB
init_design.pb 2KB
ram_utilization_synth.pb 249B
vhdl.prj 191B
ram_utilization_synth.rpt 8KB
dupFiles.rpt 88B
.vivado.begin.rst 188B
.vivado.begin.rst 183B
.vivado.end.rst 0B
.Vivado_Synthesis.queue.rst 0B
.Vivado_Synthesis.queue.rst 0B
.vivado.error.rst 0B
ram.sh 7KB
ram.sh 7KB
ram.sh 5KB
ram.sh 5KB
ram.sh 4KB
ISEWrap.sh 2KB
ISEWrap.sh 2KB
ISEWrap.sh 2KB
runme.sh 2KB
runme.sh 1KB
runme.sh 1KB
labtool_webtalk.tcl 5KB
ethernet_test.tcl 5KB
ram.tcl 4KB
ethernet_test.tcl 3KB
ethernet_test.tcl 2KB
cmd.tcl 464B
blk_mem_gen_v8_3_changelog.txt 5KB
README.txt 3KB
README.txt 2KB
README.txt 2KB
README.txt 2KB
README.txt 2KB
README.txt 2KB
htr.txt 395B
htr.txt 387B
file_info.txt 378B
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