CMOS_OV9650.rar_CMOS_OV9650_OV9650

#include <cdefBF533.h> void delay(unsigned int n) { unsigned int i; for(i=0;i<n;i++); } /*******************************sccb开始*****************************/ void sccb_start(void) { *pFIO_FLAG_S = 0x0002; delay(50); *pFIO_FLAG_S = 0x0001; delay(100); *pFIO_FLAG_C = 0x0002; delay(100); *pFIO_FLAG_C = 0x0001; delay(50); } /*********************************sccb结束*****************************/ void sccb_stop(void) { *pFIO_FLAG_C = 0x0002; delay(50); *pFIO_FLAG_S = 0x0001; delay(100); *pFIO_FLAG_S = 0x0002; delay(50); } /*********************************sccb应答*********************************/ void sccb_ack(void) { *pFIO_FLAG_S = 0x0002; delay(50); *pFIO_FLAG_S = 0x0001; delay(100); *pFIO_FLAG_C = 0x0001; delay(50); } /******************************sccb读取一个字节****************************/ unsigned char sccb_read_phase() { unsigned char ReadByte = 0; unsigned int i; *pFIO_DIR = 0xfffc; *pFIO_FLAG_S = 0x0002; delay(100); for(i=0;i<8;i++) { delay(50); *pFIO_FLAG_C = 0x0001; delay(100); *pFIO_FLAG_S = 0x0001; delay(100); ReadByte <<= 1; if(*pFIO_FLAG_S & 0x00002) ReadByte++; delay(50); } *pFIO_FLAG_C = 0x0001; delay(50); return(ReadByte); } /******************************sccb写一个字节****************************/ void sccb_write_phase(unsigned char data) { unsigned short i = 0; *pFIO_DIR = 0x0003; for (i=0; i < 8; ++i) { /*写操作*/ *pFIO_DIR = 0x0003; if(data & 0x80) //写"1" { *pFIO_FLAG_S = 0x0002; delay(50); *pFIO_FLAG_S = 0x0001; delay(100); *pFIO_FLAG_C = 0x0001; delay(50); data <<= 1; } else //写0 { *pFIO_FLAG_C = 0x0002; delay(50); *pFIO_FLAG_S = 0x0001; delay(100); *pFIO_FLAG_C = 0x0001; delay(50); data <<= 1; } } delay(50); *pFIO_FLAG_S = 0x0002; delay(100); *pFIO_FLAG_S = 0x0001; delay(50); *pFIO_FLAG_C = 0x0001; delay(50); } void sccb_write_byte(unsigned char ID_Address, unsigned char sub_Address, unsigned char data) { sccb_start(); sccb_write_phase( ID_Address ); sccb_write_phase( sub_Address ); sccb_write_phase( data ); sccb_stop(); } unsigned char sccb_read_byte(unsigned char ID_Address, unsigned char sub_Address, unsigned char ID_Address2) { unsigned char ReadByte; sccb_start(); sccb_write_phase( ID_Address ); sccb_write_phase( sub_Address ); sccb_stop(); delay(5000); sccb_start(); sccb_write_phase( ID_Address2 ); delay(100); ReadByte = sccb_read_phase(); sccb_ack(); sccb_stop(); return ReadByte; } void Init_ov9650(void) { sccb_write_byte( 0x60, 0x04, 0x00 ); /*Common Control 1 Bit[7]: Reserved Bit[6]: CCIR656 format Bit[5]: QQVGA or QQCIF format. Effective only when QVGA (register bit COM7[4]) or QCIF (register bit COM7[3]) output is selected and related HREF skip option based on format is selected (register COM1[3:2]) Bit[4]: Reserved Bit[3:2]: HREF skip option 00: No skip 01: YUV/RGB skip every other row for YUV/RGB, skip 2 rows for every 4 rows for Raw data 1x: Skip 3 rows for every 4 rows for YUV/RGB, skip 6 rows for every 8 rows for Raw data Bit[1:0]: AEC low 2 LSB (see registers AECHM for AEC[15:10] and AECH for AEC[9:2])*/ //sccb_write_byte( 0x60, 0x0c, 0x04 ); sccb_write_byte( 0x60, 0x0c, 0x00 ); /* Common Control 3 Bit[7]: Reserved Bit[6]: Output data MSB and LSB swap Bit[5:4]: Reserved Bit[3]: Pin selection 1: Change RESET pin to EXPST_B (frame exposure mode timing) and change PWDN pin to FREX (frame exposure enable) Bit[2]: VarioPixel for VGA, CIF, QVGA, QCIF, QQVGA, and QQCIF Bit[1]: Reserved Bit[0]: Single frame output (used for Frame Exposure mode only) */ //sccb_write_byte( 0x60, 0x0d, 0x80 ); sccb_write_byte( 0x60, 0x0d, 0x00 ); /*Common Control 4 Bit[7]: VarioPixel for QVGA, QCIF, QQVGA, and QQCIF Bit[6:3]: Reserved Bit[2]: Tri-state option for output clock at power-down period 0: Tri-state at this period 1: No tri-state at this period Bit[1]: Tri-state option for output data at power-down period 0: Tri-state at this period 1: No tri-state at this period Bit[0]: Reserved*/ //sccb_write_byte( 0x60, 0x11, 0x81 ); sccb_write_byte( 0x60, 0x11, 0x80 ); /*Data Format and Internal Clock Bit[7]: Digital PLL option 0: Disable double clock option, meaning the maximum PCLK can be as high as half input clock 1: Enable double clock option, meaning the maximum PCLK can be as high as input clock Bit[6]: Use input clock directly (no clock pre-scale available) Bit[5:0]: Internal clock pre-scalar F(internal clock) = F(input clock)/(Bit[5:0]+1) � Range: [0 0000] to [1 1111]*/ //sccb_write_byte( 0x60, 0x12, 0x40 ); sccb_write_byte( 0x60, 0x12, 0x00 ); /*Common Control 7 Bit[7]: SCCB Register Reset 0: No change 1: Resets all registers to default values Bit[6]: Output format - VGA selection Bit[5]: Output format - CIF selection Bit[4]: Output format - QVGA selection Bit[3]: Output format - QCIF selection