DCMI_OV9655.rar_DCMI_camera_ov9655

/** ****************************************************************************** * @file stm32f4xx_rcc.c * @author MCD Application Team * @version V1.0.0 * @date 30-September-2011 * @brief This file provides firmware functions to manage the following * functionalities of the Reset and clock control (RCC) peripheral: * - Internal/external clocks, PLL, CSS and MCO configuration * - System, AHB and APB busses clocks configuration * - Peripheral clocks configuration * - Interrupts and flags management * * @verbatim * * =================================================================== * RCC specific features * =================================================================== * * After reset the device is running from Internal High Speed oscillator * (HSI 16MHz) with Flash 0 wait state, Flash prefetch buffer, D-Cache * and I-Cache are disabled, and all peripherals are off except internal * SRAM, Flash and JTAG. * - There is no prescaler on High speed (AHB) and Low speed (APB) busses; * all peripherals mapped on these busses are running at HSI speed. * - The clock for all peripherals is switched off, except the SRAM and FLASH. * - All GPIOs are in input floating state, except the JTAG pins which * are assigned to be used for debug purpose. * * Once the device started from reset, the user application has to: * - Configure the clock source to be used to drive the System clock * (if the application needs higher frequency/performance) * - Configure the System clock frequency and Flash settings * - Configure the AHB and APB busses prescalers * - Enable the clock for the peripheral(s) to be used * - Configure the clock source(s) for peripherals which clocks are not * derived from the System clock (I2S, RTC, ADC, USB OTG FS/SDIO/RNG) * * @endverbatim * ****************************************************************************** * @attention * * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS. * * <h2><center>&copy; COPYRIGHT 2011 STMicroelectronics</center></h2> ****************************************************************************** */ /* Includes ------------------------------------------------------------------*/ #include "stm32f4xx_rcc.h" /** @addtogroup STM32F4xx_StdPeriph_Driver * @{ */ /** @defgroup RCC * @brief RCC driver modules * @{ */ /* Private typedef -----------------------------------------------------------*/ /* Private define ------------------------------------------------------------*/ /* ------------ RCC registers bit address in the alias region ----------- */ #define RCC_OFFSET (RCC_BASE - PERIPH_BASE) /* --- CR Register ---*/ /* Alias word address of HSION bit */ #define CR_OFFSET (RCC_OFFSET + 0x00) #define HSION_BitNumber 0x00 #define CR_HSION_BB (PERIPH_BB_BASE + (CR_OFFSET * 32) + (HSION_BitNumber * 4)) /* Alias word address of CSSON bit */ #define CSSON_BitNumber 0x13 #define CR_CSSON_BB (PERIPH_BB_BASE + (CR_OFFSET * 32) + (CSSON_BitNumber * 4)) /* Alias word address of PLLON bit */ #define PLLON_BitNumber 0x18 #define CR_PLLON_BB (PERIPH_BB_BASE + (CR_OFFSET * 32) + (PLLON_BitNumber * 4)) /* Alias word address of PLLI2SON bit */ #define PLLI2SON_BitNumber 0x1A #define CR_PLLI2SON_BB (PERIPH_BB_BASE + (CR_OFFSET * 32) + (PLLI2SON_BitNumber * 4)) /* --- CFGR Register ---*/ /* Alias word address of I2SSRC bit */ #define CFGR_OFFSET (RCC_OFFSET + 0x08) #define I2SSRC_BitNumber 0x17 #define CFGR_I2SSRC_BB (PERIPH_BB_BASE + (CFGR_OFFSET * 32) + (I2SSRC_BitNumber * 4)) /* --- BDCR Register ---*/ /* Alias word address of RTCEN bit */ #define BDCR_OFFSET (RCC_OFFSET + 0x70) #define RTCEN_BitNumber 0x0F #define BDCR_RTCEN_BB (PERIPH_BB_BASE + (BDCR_OFFSET * 32) + (RTCEN_BitNumber * 4)) /* Alias word address of BDRST bit */ #define BDRST_BitNumber 0x10 #define BDCR_BDRST_BB (PERIPH_BB_BASE + (BDCR_OFFSET * 32) + (BDRST_BitNumber * 4)) /* --- CSR Register ---*/ /* Alias word address of LSION bit */ #define CSR_OFFSET (RCC_OFFSET + 0x74) #define LSION_BitNumber 0x00 #define CSR_LSION_BB (PERIPH_BB_BASE + (CSR_OFFSET * 32) + (LSION_BitNumber * 4)) /* ---------------------- RCC registers bit mask ------------------------ */ /* CFGR register bit mask */ #define CFGR_MCO2_RESET_MASK ((uint32_t)0x07FFFFFF) #define CFGR_MCO1_RESET_MASK ((uint32_t)0xF89FFFFF) /* RCC Flag Mask */ #define FLAG_MASK ((uint8_t)0x1F) /* CR register byte 3 (Bits[23:16]) base address */ #define CR_BYTE3_ADDRESS ((uint32_t)0x40023802) /* CIR register byte 2 (Bits[15:8]) base address */ #define CIR_BYTE2_ADDRESS ((uint32_t)(RCC_BASE + 0x0C + 0x01)) /* CIR register byte 3 (Bits[23:16]) base address */ #define CIR_BYTE3_ADDRESS ((uint32_t)(RCC_BASE + 0x0C + 0x02)) /* BDCR register base address */ #define BDCR_ADDRESS (PERIPH_BASE + BDCR_OFFSET) /* Private macro -------------------------------------------------------------*/ /* Private variables ---------------------------------------------------------*/ static __I uint8_t APBAHBPrescTable[16] = {0, 0, 0, 0, 1, 2, 3, 4, 1, 2, 3, 4, 6, 7, 8, 9}; /* Private function prototypes -----------------------------------------------*/ /* Private functions ---------------------------------------------------------*/ /** @defgroup RCC_Private_Functions * @{ */ /** @defgroup RCC_Group1 Internal and external clocks, PLL, CSS and MCO configuration functions * @brief Internal and external clocks, PLL, CSS and MCO configuration functions * @verbatim =============================================================================== Internal/external clocks, PLL, CSS and MCO configuration functions =============================================================================== This section provide functions allowing to configure the internal/external clocks, PLLs, CSS and MCO pins. 1. HSI (high-speed internal), 16 MHz factory-trimmed RC used directly or through the PLL as System clock source. 2. LSI (low-speed internal), 32 KHz low consumption RC used as IWDG and/or RTC clock source. 3. HSE (high-speed external), 4 to 26 MHz crystal oscillator used directly or through the PLL as System clock source. Can be used also as RTC clock source. 4. LSE (low-speed external), 32 KHz oscillator used as RTC clock source. 5. PLL (clocked by HSI or HSE), featuring two different output clocks: - The first output is used to generate the high speed system clock (up to 168 MHz) - The second output is used to generate the clock for the USB OTG FS (48 MHz), the random analog generator (<=48 MHz) and the SDIO (<= 48 MHz). 6. PLLI2S (clocked by HSI or HSE), used to generate an accurate clock to achieve high-quality audio performance