RK3288 TRM
FuZhou Rockchip Electronics Co.,Ltd. 21
Chapter 1 Introduction
RK3288 is a low power, high performance processor for mobile phones, personal mobile
internet device and other digital multimedia applications, and integrates quad-core
Cortex-A17 with separately NEON coprocessor.
Many embedded powerful hardware engines provide optimized performance for high-end
application. RK3288 supports almost full-format H.264 decoder by 2160p@24fps, H.265
decoder by 2160p@60fps, also support H.264/MVC/VP8 encoder by 1080p@30fps,
high-quality JPEG encoder/decoder, special image preprocessor and postprocessor.
Embedded 3D GPU makes RK3288 completely compatible with OpenGL ES1.1/2.0/3.0,
OpenCL 1.1 and DirectX 11. Special 2D hardware engine with MMU will maximize display
performance and provide very smoothly operation.
RK3288 has high-performance dual channel external memory interface(DDR3/DDR3L
/LPDDR2/LPDDR3) capable of sustaining demanding memory bandwidths, also provides a
complete set of peripheral interface to support very flexible applications..
1.1 Features
1.1.1 MicroProcessor
l Quad-core ARM Cortex-A17 MPCore processor, a high-performance, low-power and
cached application processor
l Full implementation of the ARM architecture v7-A instruction set, ARM Neon Advanced
SIMD (single instruction, multiple data) support for accelerated media and signal
processing computation
l Superscalar, variable length, out-of-order pipeline with dynamic branch prediction,
8-stage pipeline
l Include VFP v3 hardware to support single and double-precision add, subtract, divide,
multiply and accumulate, and square root operations
l SCU ensures memory coherency between the four CPUs
l Integrated 32KB L1 instruction cache , 32KB L1 data cache with 4-way set associative
l 1MB unified L2 Cache
l Trustzone technology support
l Full coresight debug solution
n Debug and trace visibility of whole systems
n ETM trace support
n Invasive and non-invasive debug
l Six separate power domains for every core to support internal power switch and
externally turn on/off based on different application scenario
n PD_A17_0: 1
st
Cortex-A17 + Neon + FPU + L1 I/D Cache
n PD_A17_1: 2
nd
Cortex-A17 + Neon + FPU + L1 I/D Cache
n PD_A17_2: 3
rd
Cortex-A17 + Neon + FPU + L1 I/D Cache
n PD_A17_3: 4
th
Cortex-A17 + Neon + FPU + L1 I/D Cache
n PD_SCU: SCU + L2 Cache controller, and including PD_A17_0, PD_A17_1, PD_A17_2,
PD_A17_3, debug logic
l One isolated voltage domain to support DVFS
l Maximum frequency can be up to 1GHz@1.0V
1.1.2 Memory Organization
l Internal on-chip memory
n 20KB BootRom
n 100KB internal SRAM for security and non-security access, detailed size is
programmable
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