library IEEE;
use IEEE.std_logic_1164.all;
entity Vdlatch is
port(
D,C:in std_logic;
Qn :out std_logic;
Q:out std_logic
);
end Vdlatch;
architecture Vdlatch_s of Vdlatch is
signal Qout:std_logic;
begin
process(C,D,Qout)
begin
if(C='1') then Qout<=D;
else Qout<=Qout;
end if;
Q<=Qout;Qn<= not Qout;
end process;
end Vdlatch_s;