latch
library ieee;
use ieee.std_logic_1164.all;
entity Latch1 is
port(a:in std_logic;
ena:in std_logic;
q:out std_logic);
end Latch1;
architecture example of Latch1 is
begin
process(a,ena)
begin
if ena='0' then
q<=a;
end if;
end process;
end example;
library ieee;
use ieee.std_logic_1164.all;
package my_pkg is
component Latch1
port(a:in std_logic;
ena:in std_logic;
q:out std_logic);
end component;
end package;
library ieee;
use ieee.std_logic_1164.all;
use work.my_pkg.all;
entity Latch8 is
port(a:in std_logic_vector(7 downto 0);
clr:in bit;
ena:std_logic;
q:out std_logic_vector(7 downto 0));
end Latch8;
architecture one of Latch8 is
signal sig_save:std_logic_vector(7 downto 0);
begin GeLatch:
for n in 0 to 7 GENERATE
Latchx:Latch1 port MAP(a(n),ena,sig_save(n));
end GENERATE;
q<=sig_save when clr='1' else
"11111111";
end one;