OpenCores GPIO IP Core 3/4/01
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PWM/Timer/Counter
IP Core
Specification
Author: Damjan Lampret
lampret@opencores.org
Rev. 0.1
February 28, 2001
Preliminary Draft
OpenCores GPIO IP Core 3/4/01
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Revision History
Rev. Date Author Description
0.1 28/2/01
Damjan Lampret First Draft
OpenCores GPIO IP Core 3/4/01
www.opencores.org Rev 0.2 Preliminary 3 of 17
Table Of Contents
Introduction.........................................................................................................................6
Features..........................................................................................................................6
Architecture........................................................................................................................7
Clocks.............................................................................................................................7
WISHBONE Interface ....................................................................................................8
PTC Registers.................................................................................................................8
PTC Circuitry.................................................................................................................8
Interface to External I/O Cells and Pads.........................................................................8
Operation............................................................................................................................9
Hardware Reset............................................................................................................10
PWM Mode..................................................................................................................10
Timer/Counter Mode....................................................................................................10
Gate Feature .................................................................................................................11
Interrupt Feature ...........................................................................................................11
Capture Feature ............................................................................................................11
Registers...........................................................................................................................12
Registers list.................................................................................................................12
Register RPTC_CNTR description..............................................................................12
Register RPTC_HRC description.................................................................................12
Register RPTC_LRC description.................................................................................13
Register RPTC_CTRL description...............................................................................13
IO ports.............................................................................................................................15
WISHBONE host interface...........................................................................................15
Interface to external I/O cells and pads ........................................................................16
Core HW Configuration....................................................................................................17
OpenCores GPIO IP Core 3/4/01
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Table Of Figures
Figure 1. Core’s Architecture.............................................................................................7
Figure 2. Block Diagram of PTC Logic..............................................................................9
Figure 3. Core’s Interfaces...............................................................................................15
OpenCores GPIO IP Core 3/4/01
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Table Of Tables
Table 1. List of All Software Accessible Registers.........................................................12
Table 2. Main PTC Counter..............................................................................................12
Table 3. RPTC_HRC Register .........................................................................................13
Table 4. RPTC_LRC Register..........................................................................................13
Table 5. Control Register.................................................................................................14
Table 6. WISHBONE Interface’ Signals..........................................................................16
Table 7. External interface ...............................................................................................16
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