8_uart_test.zip_quartus uart_uart_uart quartus _verilog中8.1uart_

+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ ; Legal Partition Candidates ; +-----------+-------+----------------+--------------+----------------+--------+-----------------+---------------+-----------------+-------+----------------+--------------+------------------+-------------------+ ; Hierarchy ; Input ; Constant Input ; Unused Input ; Floating Input ; Output ; Constant Output ; Unused Output ; Floating Output ; Bidir ; Constant Bidir ; Unused Bidir ; Input only Bidir ; Output only Bidir ; +-----------+-------+----------------+--------------+----------------+--------+-----------------+---------------+-----------------+-------+----------------+--------------+------------------+-------------------+ ; inst1 ; 3 ; 2 ; 0 ; 2 ; 11 ; 2 ; 2 ; 2 ; 0 ; 0 ; 0 ; 0 ; 0 ; ; inst ; 2 ; 0 ; 0 ; 0 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; ; inst2 ; 11 ; 1 ; 0 ; 1 ; 2 ; 1 ; 1 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; +-----------+-------+----------------+--------------+----------------+--------+-----------------+---------------+-----------------+-------+----------------+--------------+------------------+-------------------+