+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Legal Partition Candidates ;
+------------------+-------+----------------+--------------+----------------+--------+-----------------+---------------+-----------------+-------+----------------+--------------+------------------+-------------------+
; Hierarchy ; Input ; Constant Input ; Unused Input ; Floating Input ; Output ; Constant Output ; Unused Output ; Floating Output ; Bidir ; Constant Bidir ; Unused Bidir ; Input only Bidir ; Output only Bidir ;
+------------------+-------+----------------+--------------+----------------+--------+-----------------+---------------+-----------------+-------+----------------+--------------+------------------+-------------------+
; Uart_Tx_Init ; 12 ; 0 ; 0 ; 0 ; 2 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ;
; Uart_Tx_Bps_Init ; 3 ; 0 ; 0 ; 0 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ;
; Uart_Rx_Init ; 4 ; 0 ; 0 ; 0 ; 9 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ;
; Uart_Rx_Bps_Init ; 3 ; 0 ; 0 ; 0 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ;
+------------------+-------+----------------+--------------+----------------+--------+-----------------+---------------+-----------------+-------+----------------+--------------+------------------+-------------------+
Project_Uart.zip_3V7L_fpga_further6aa_verilog
版权申诉
78 浏览量
2022-09-15
02:03:57
上传
评论
收藏 3.06MB ZIP 举报
Project_Uart.zip_3V7L_fpga_further6aa_verilog （104个子文件） 
Project_Uart.root_partition.cmp.ammdb 403B Project_Uart.vpr.ammdb 364B Project_Uart.map.ammdb 129B Project_Uart.cmp.bpm 662B Project_Uart.map.bpm 636B Project_Uart.cmp.cdb 21KB Project_Uart.root_partition.cmp.cdb 10KB Project_Uart.map.cdb 9KB Project_Uart.root_partition.map.cdb 9KB Project_Uart.sgdiff.cdb 9KB Project_Uart.rtlv_sg.cdb 7KB Project_Uart.(2).cnf.cdb 3KB Project_Uart.(3).cnf.cdb 3KB Project_Uart.(1).cnf.cdb 2KB Project_Uart.(0).cnf.cdb 2KB Project_Uart.map_bb.cdb 2KB Project_Uart.root_partition.map.hbdb.cdb 1KB Project_Uart.rtlv_sg_swap.cdb 1KB Project_Uart.root_partition.map.reg_db.cdb 226B logic_util_heursitic.dat 6KB Project_Uart.db_info 140B Project_Uart.db_info 140B Project_Uart.tiscmp.slow_1200mv_0c.ddb 132KB Project_Uart.tiscmp.slow_1200mv_85c.ddb 132KB Project_Uart.tiscmp.fast_1200mv_0c.ddb 130KB Project_Uart.tiscmp.fastest_slow_1200mv_85c.ddb 106KB Project_Uart.tiscmp.fastest_slow_1200mv_0c.ddb 106KB Project_Uart.asm_labs.ddb 8KB Project_Uart.tis_db_list.ddb 310B Project_Uart.pti_db_list.ddb 246B Project_Uart.root_partition.cmp.dfp 33B Project_Uart.done 26B Project_Uart.root_partition.map.dpi 1002B Project_Uart.root_partition.map.hbdb.hb_info 46B Project_Uart.cmp.hdb 13KB Project_Uart.root_partition.cmp.hdb 13KB Project_Uart.root_partition.map.hdb 12KB Project_Uart.map.hdb 12KB Project_Uart.pre_map.hdb 12KB Project_Uart.root_partition.map.hbdb.hdb 12KB Project_Uart.sgdiff.hdb 12KB Project_Uart.rtlv.hdb 12KB Project_Uart.map_bb.hdb 9KB Project_Uart.(2).cnf.hdb 1KB Project_Uart.(3).cnf.hdb 1KB Project_Uart.(0).cnf.hdb 1KB Project_Uart.(1).cnf.hdb 987B Project_Uart.hier_info 6KB Project_Uart.hif 666B Project_Uart.cycloneive_io_sim_cache.45um_ff_1200mv_0c_fast.hsd 728KB Project_Uart.cycloneive_io_sim_cache.45um_ss_1200mv_0c_slow.hsd 727KB Project_Uart.cycloneive_io_sim_cache.45um_ss_1200mv_85c_slow.hsd 723KB
Project_Uart.lpc.html 1KB Project_Uart.cmp.idb 3KB Project_Uart.ipinfo 163B Project_Uart.jdi 230B Project_Uart.root_partition.map.kpt 2KB Project_Uart.map.kpt 2KB Project_Uart.cmp_merge.kpt 215B .cmp.kpt 207B Project_Uart.cmp.logdb 8KB Project_Uart.map_bb.logdb 4B Project_Uart.map.logdb 4B Project_Uart.root_partition.cmp.logdb 4B Project_Uart.pin 20KB prev_cmp_Project_Uart.qmsg 45KB Project_Uart.sta.qmsg 16KB Project_Uart.fit.qmsg 16KB Project_Uart.map.qmsg 9KB Project_Uart.asm.qmsg 2KB Project_Uart.qpf 1KB Project_Uart.qsf 4KB Project_Uart.qws 48B Project_Uart.root_partition.cmp.rcfdb 9KB Project_Uart.sta.rdb 19KB Project_Uart.cmp.rdb 17KB Project_Uart.routing.rdb 4KB Project_Uart.asm.rdb 1KB Project_Uart.map.rdb 1KB Project_Uart.lpc.rdb 508B Project_Uart.pplq.rdb 296B README 653B Project_Uart.sta.rpt 198KB Project_Uart.fit.rpt 109KB Project_Uart.map.rpt 27KB Project_Uart.flow.rpt 8KB Project_Uart.asm.rpt 7KB Project_Uart.sld_design_entry_dsc.sci 277B Project_Uart.sld_design_entry.sci 277B Project_Uart.root_partition.map.hbdb.sig 32B Project_Uart.fit.smsg 703B Project_Uart.sof 350KB Project_Uart.sta.summary 986B Project_Uart.fit.summary 612B Project_Uart.map.summary 477B Project_Uart.sta_cmp.8_slow_1200mv_85c.tdb 23KB Project_Uart.tmw_info 259B
Project_Uart.lpc.txt 2KB Project_Uart.smart_action.txt 6B Uart_Tx_Module.v 6KB共 104 条
- 1
- 2
评论0