OpenCores SPI Master Core Specification 9/23/2022
www.opencores.org Rev 0.5 i
Revision History
Rev.
Date
Author
Description
0.1
June 13, 2002
Simon Srot
First Draft
0.2
July 12, 2002
Simon Srot
Document is lectured.
0.3
December 28,
2002
Simon Srot
Support for 64 bit character len added.
0.4
March 26,
2003
Simon Srot
Automatic slave select signal generation added.
0.5
April 15 2003
Simon Srot
Support for 128 bit character len added.
0.6
March 15,
2004
Simon Srot
Bit fields in CTRL changed.
OpenCores SPI Master Core Specification 9/23/2022
www.opencores.org Rev 0.5 ii
Contents
CONTENTS...........................................................................................................II
INTRODUCTION..................................................................................................1
IO PORTS...............................................................................................................2
2.1 WISHBONE INTERFACE SIGNALS...................................................................2
2.2 SPI EXTERNAL CONNECTIONS..........................................................................2
REGISTERS...........................................................................................................3
3.1 CORE REGISTERS LIST .....................................................................................3
3.2 DATA RECEIVE REGISTER LOW/HIGH[RXL/RXH].............................................3
3.3 DATA TRANSMIT REGISTER LOW/HIGH[TXL/TXH] ..........................................4
3.4 CONTROL AND STATUS REGISTER [CTRL].......................................................4
3.5 DIVIDER REGISTER [DIVIDER].......................................................................5
3.6 SLAVE SELECT REGISTER [SS] .........................................................................5
OPERATION..........................................................................................................7
4.1 WISHBONE INTERFACE.................................................................................7
4.2 SERIAL INTERFACE ..........................................................................................7
ARCHITECTURE .................................................................................................9
CORE CONFIGURATION ................................................................................10
OpenCores SPI Master Core Specification 9/23/2022
www.opencores.org Rev 0.6 1 of 10
1
Introduction
This document provides specifications for the SPI (Serial Peripheral Interface) Master
core. Synchronous serial interfaces are widely used to provide economical board-level
interfaces between different devices such as microcontrollers, DACs, ADCs and
other. Although there is no single standard for a synchronous serial bus, there are
industry-wide accepted guidelines based on two most popular implementations:
� SPI (a trademark of Motorola Semiconductor)
� Microwire/Plus (a trademark of National Semiconductor)
Many IC manufacturers produce components that are compatible with SPI and
Microwire/Plus.
The SPI Master core is compatible with both above-mentioned protocols as master
with some additional functionality. At the hosts side, the core acts like a WISHBONE
compliant slave device.
Features:
� Full duplex synchronous serial data transfer
� Variable length of transfer word up to 128 bits
� MSB or LSB first data transfer
� Rx and Tx on both rising or falling edge of serial clock independently
� 8 slave select lines
� Fully static synchronous design with one clock domain
� Technology independent Verilog
� Fully synthesizable
