Logical project decsription
core - external not under development IP cores
doc - project documentation
include - common rtl, testbench header files
rtl - rtl models of project units
sim - simulation scripts for verivication
testbench - verification enviroment for project
fsmc.zip_STM32 FSMC_fsmc_stm32 fsmc sdram
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2022-09-14
19:40:26
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fsmc.zip （40个子文件） 
fsmc 
fsmc.ucf 4KB fpga_test_fsmc.vhd 4KB hssdrc tags branches web_uploads trunk core mt48lc2m32b2.v 48KB test.v 12KB include hssdrc_define.vh 7KB hssdrc_timing.vh 5KB hssdrc_timescale.vh 2KB tb_define.svh 5KB hssdrc_tb_sys_if.vh 4KB rtl hssdrc_mux.v 5KB hssdrc_addr_path_p1.v 7KB hssdrc_data_path_p1.v 13KB hssdrc_decoder.v 17KB hssdrc_refr_counter.v 4KB hssdrc_top.v 30KB hssdrc_decoder_state.v 17KB hssdrc_access_manager.v 25KB hssdrc_ba_map.v 4KB hssdrc_arbiter_in.v 7KB hssdrc_init_state.v 5KB hssdrc_data_path.v 13KB hssdrc_addr_path.v 7KB hssdrc_arbiter_out.v 22KB testbench tb_prog.sv 15KB tb_top.sv 5KB sdram_transaction_class.sv 7KB hssdrc_driver_class.sv 9KB sdram_agent_class.sv 4KB sdram_interpretator.sv 3KB sdram_tread_class.sv 3KB hssrdc_bandwidth_monitor_class.sv 6KB hssrdc_driver_cbs_class.sv 2KB message_class.sv 3KB hssrdc_scoreboard_class.sv 4KB sim sim.do 5KB compile.do 2KB doc hssdrc_design_document_rev10.odt 80KB
hssdrc_design_document.pdf 310KB
readme.txt 308B system_stm32f4.c 6KB
JaniceLu
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